RAM 7.0 Betriebsanweisung PDF herunterladen (Seite 96)

LogiCORE IP Block Memory Generator v6.1

96 www.xilinx.com DS512 March 1, 2011

Product Specification

Output Register Configurations

The Block Memory Generator core provides optional output registers that can be selected for port A

and port B separately, and that may improve the performance of the core. The configurations described

in the sections that follow are separated into these sections:

• Kintex-7, Virtex-7, Virtex-6, Virtex-5, and Virtex-4 Devices

• Spartan-6 and Spartan-3A DSP Devices

• Spartan-3 Devices and Implementations

Figure 63 shows the Optional Output Registers section of the Block Memory Generator GUI.

Kintex-7, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 FPGA: Output Register

Configurations

To tailor register options for Kintex-7, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 FPGA configurations,

two selections for port A and two selections for port B are provided on Screen 3 of the CORE Generator

GUI in the Optional Output Registers section. The embedded output registers for the corresponding

port(s) are enabled when Register Port [A|B] Output of Memory Primitives is selected. Similarly,

registers at the output of the core for the corresponding port(s) are enabled by selecting Register Port

[A|B] Output of Memory Core. Figure 64 through Figure 71 illustrate the Kintex-7, Virtex-7, Virtex-6,

Virtex-5 and Virtex-4 FPGA output register configurations.

X-Ref Target - Figure 63

Figure 63: Optional Output Registers Section

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RAM 7.0 Betriebsanweisung Seite 96