RAM 7.0 Betriebsanweisung PDF herunterladen (Seite 81)

DS512 March 1, 2011 www.xilinx.com 81

Product Specification

LogiCORE IP Block Memory Generator v6.1

Algorithm

The differences between the minimum area, low power and fixed primitive algorithms are discussed in

detail in Selectable Memory Algorithm, page 4. Table 33 shows examples of the resource utilization and

the performance difference between them for two selected configurations for Virtex-6 FPGA

architectures.

Table 34 shows examples of the resource utilization and the performance difference between them for

two selected configurations for Virtex-5 FPGA architecture.

2. Read port is 136x640; Write port is 17x5k.

Table 33: Memory Algorithm Examples Virtex-6 Devices

Memory

Type

Width x

Depth

Algorithm

Type

Block RAM

Shift Regs FFs LUTs

(1)

1. LUTs are reported as the number of 4-input LUTs, and do not reflect the number of LUTs used as a route-through.

Performance

(MHz)

36K 16K 8K

Single-port

RAM

17x5k

Minimum area 1 3 0 0 3 18 325

Fixed Primitive

using 18x1k

block RAM

2 1 0 0 3 19 300

Low power 0 5 0 0 3 37 275

36x4k

Minimum area 4 0 0 0 0 0 325

Fixed Primitive

using 36x512

block RAM

4 0 0 0 2 38 275

Low power 4 0 0 0 3 76 275

Table 34: Memory Algorithm Examples Virtex-5 Devices

Memory

Type

Width x

Depth

Algorithm

Type

Block RAM

Shift Regs FFs LUTs

(1)

1. LUTs are reported as the number of 4-input LUTs, and do not reflect the number of LUTs used as a route-through.

Performance

(MHz)

36K 16K 8K

Single-port

RAM

17x5k

Minimum area 1 3 0 0 3 18 300

Fixed Primitive

using 18x1k

block RAM

2 1 0 0 3 20 300

Low power 0 5 0 0 3 39 275

36x4k

Minimum area 4 0 0 0 0 0 300

Fixed Primitive

using 36x512

block RAM

4 0 0 0 2 40 275

Low power 0 8 0 0 3 80 250

1 2 ... 76 77 78 79 80 81 82 83 84 85 86 ... 117 118

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