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DS512 March 1, 2011 www.xilinx.com 89

Product Specification

LogiCORE IP Block Memory Generator v6.1

C_HAS_MUX_OUTPUT_RE

GS_A

Integer 0,1

Determines whether port A has a

the memory core

C_HAS_MUX_OUTPUT_RE

GS_B

Integer 0,1

Determines whether port B has a

the memory core

20 C_MUX_PIPELINE_STAGES Integer 0,1,2,3

Determines the number of pipeline

stages within the MUX for both port

A and port B

21 C_WRITE_WIDTH_A Integer 1 to 1152 Defines width of Write port A

22 C_READ_WIDTH_A Integer 1 to 1152 Defines width of Read port A

23 C_WRITE_DEPTH_A Integer 2 to 9011200 Defines depth of Write port A

24 C_READ_DEPTH_A Integer 2 to 9011200 Defines depth of Read port A

25 C_ADDRA_WIDTH Integer 1 to 24 Defines the width of address A

26 C_WRITE_MODE_A String

Write_First, Read_first,

No_change

Defines the Write mode for port A

27 C_HAS_ENA Integer 0, 1

Determines whether port A has an

enable pin

28 C_HAS_REGCEA Integer 0, 1

Determines whether port A has an

enable pin for its output register

29 C_HAS_RSTA Integer 0, 1

Determines whether port A has

reset pin

30 C_INITA_VAL String "0"

Defines initialization/power-on value

for port A output

31 C_USE_BYTE_WEA Integer 0, 1

Determines whether byte-Write

feature is used on port A

For True Dual Port configurations,

this value is the same as

C_USE_BYTE_WEB, since there is

only a single byte Write enable

option provided

32 C_WEA_WIDTH Integer 1 to 128 Defines width of WEA pin for port A

33 C_WRITE_WIDTH_B Integer 1 to 1152 Defines width of Write port B

34 C_READ_WIDTH_B Integer 1 to 1152 Defines width of Read port B

35 C_WRITE_DEPTH_B Integer 2 to 9011200 Defines depth of Write port B

36 C_READ_DEPTH_B Integer 2 to 9011200 Defines depth of Read port B

37 C_ADDRB_WIDTH Integer 1 to 24 Defines the width of address B

38 C_WRITE_MODE_B String

Write_First, Read_first,

No_change

Defines the Write mode for port B

39 C_HAS_ENB Integer 0, 1

Determines whether port B has an

enable pin

40 C_HAS_REGCEB Integer 0, 1

Determines whether port B has an

enable pin for its output register

41 C_HAS_RSTB Integer 0, 1

Determines whether port B has

reset pin

Table 43: Native Interface SIM Parameters (Cont’d)

SIM Parameter Type Values Description

1 2 ... 84 85 86 87 88 89 90 91 92 93 94 ... 117 118

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