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LogiCORE IP Block Memory Generator v6.1

6 www.xilinx.com DS512 March 1, 2011

Product Specification

AXI4 Interface Block Memory Generator Feature Summary

Overview

AXI4 Interface Block Memories are built on the Native Interface Block Memories (see Figure 1). Two

AXI4 interface styles are available - AXI4 and AXI4-Lite. The core can also be further classified as a

Memory Slave or as a Peripheral Slave. In addition to applications supported by the Native Interface

Block Memories, AXI4 Block Memories can also be used in AXI4 System Bus applications and Point-to-

Point applications.

All communication in the AXI protocol is performed using five independent channels. Each of the five

independent channels consists of a set of information signals and uses a two-way VALID and READY

handshake mechanism. The information source uses the VALID signal to show when valid data or

control information is available on the channel. The information destination uses the READY signal to

show when it can accept the data.

In Figure 2, the information source generates the VALID signal to indicate when data is available.

The destination generates the READY signal to indicate that it can accept the data, and transfer occurs

only when both the VALID and READY signals are high.

The AXI4 Block Memory Generator is an AXI4 endpoint Slave IP and can communicate with multiple

AXI4 Masters in an AXI4 System or with Standalone AXI4 Masters in point to point applications. The

core supports Simple Dual Port RAM configurations. Because AXI4 Block Memories are built using

Native interface Block Memories, they share many common features.

X-Ref Target - Figure 1

Figure 1: AXI4 Interface BMG Block Diagram

X-Ref Target - Figure 2

Figure 2: AXI4 Interface Handshake Timing Diagram

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