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LogiCORE IP Block Memory Generator v6.1

62 www.xilinx.com DS512 March 1, 2011

Product Specification

Generating the Block Memory Generator Core

Generating the Native Block Memory Generator Core

The Block Memory Generator is available from the CORE Generator software. To open the Block

Memory core from the main CORE Generator window, do the following:

Click View by Function > Memories & Storage Elements > RAMs & ROMs

The following section defines the maximum possible customization options in the Block Memory

Generator GUI screens. The actual GUI screens with enabled options will depend on the user

configuration.

CORE Generator Parameter Screens

The Native interface Block Memory Generator GUI includes six main screens:

• Interface Type Selection Screen

S_AXI_ARVALID Input

Read Address Valid. This signal indicates, when HIGH, that the Read

address and control information is valid and will remain stable until the

address acknowledge signal, ARREADY, is high.

1 = address and control information valid

0 = address and control information not valid

S_AXI_ARREADY Output

Read Address Ready. This signal indicates that the slave is ready to accept

an address and associated control signals:

1 = slave ready

0 = slave not ready

AXI4-Lite Read Data Channel Interface Signals

S_AXI_RDATA[m-1:0] Output

Read Data. For Memory Slave configurations, the Read data bus can be 32

or 64 bits wide. For Peripheral Slave configurations, the Read data bus can

be 8, 16, 32 or 64 bits wide.

S_AXI_RRESP[1:0] Output

Read Response. This signal indicates the status of the Read transfer. The

allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.

Read response is always set to OKAY.

Read response is generated only when AXI4 ID is enabled for Memory

Slave. Read response is not supported for Peripheral Slave configuration.

S_AXI_RID[m:0] Output

Read ID Tag. This signal is the ID tag of the Read data group of signals. The

RID value is generated by the slave and must match the ARID value of the

Read transaction to which it is responding.

Read ID tag is optional for Memory Slave configuration and is not supported

for Peripheral Slave configuration.

Read ID tag can be 1 to 16 bits wide.

S_AXI_RVALID Output

Read Valid. This signal indicates that the required Read data is available

and the Read transfer can complete:

1 = Read data available

0 = Read data not available

S_AXI_RREADY Input

Read Ready. This signal indicates that the master can accept the Read data

and response information:

1= Master ready

0 = Master not ready

Table 21: AXI4-Lite Read Channel Interface Signals (Cont’d)

Name Direction Description

1 2 ... 57 58 59 60 61 62 63 64 65 66 67 ... 117 118

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