RAM 7.0 Betriebsanweisung PDF herunterladen (Seite 32)

LogiCORE IP Block Memory Generator v6.1

32 www.xilinx.com DS512 March 1, 2011

Product Specification

define the Write-to-Read relationship of the A or B ports, and only impact the relationship between A

and B ports during an address collision.

For Synchronous Clocking and during a collision, the Write mode of port A can be configured so that a

Read operation on port B either produces data (acting like READ_FIRST), or produces undefined data

(Xs). For this reason, the core is hard-coded to produce READ_FIRST-like behavior when configured as

a Simple Dual-port RAM. For detailed information about this behavior, see Collision Behavior, page 30.

Exceptions: For Kintex-7, Virtex-7, Virtex-6, and Spartan-6 devices, the operating mode (READ_FIRST

or WRITE_FIRST respectively) is determined by whether the clocking mode selection is Synchronous

(Common Clock) or Asynchronous. See Clocking Options, page 65 for more details.

Additional Memory Collision Restrictions: Address Space Overlap

Kintex-7, Virtex-7, Virtex-6 and Spartan-6 FPGA block RAM memories have additional collision

restrictions in the following configurations:

• When configured as True Dual Port (TDP)

• When CLKA (port A) and CLKB (port B) are Asynchronous

• In applications that perform a simultaneous Read and Write

• When either port A, port B, or both ports are configured with Write Mode configured as

READ_FIRST

When using TDP Memory with Write Mode = READ_FIRST (TDP-RF mode) in conjunction with

asynchronous clocking, see the “Conflict Avoidance” section of the 7 Series FPGAs Memory Resources

User Guide (UG473), the Virtex-6 FPGA Memory Resources User Guide (UG363

) or the Spartan-6 FPGA

Block RAM Resources User Guide (UG383

For Kintex-7, Virtex-7, Virtex-6 and Spartan-6 devices using the TDP-RF mode, the Address Space

Overlap issue must be considered.

Optional Output Registers

The Block Memory Generator allows optional output registers, which may improve the performance of

the core. The user may choose to include register stages at two places: at the output of the block RAM

primitives and at the output of the core.

Registers at the output of the block RAM primitives reduce the impact of the clock-to-out delay of the

primitives. Registers at the output of the core isolate the delay through the output multiplexers,

improving the clock-to-out delay of the Block Memory Generator core. Each of the two optional register

stages can be chosen for port A and port B separately. Note that each optional register stage used adds

an additional clock cycle of latency to the Read operation.

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RAM 7.0 Betriebsanweisung Seite 32