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LogiCORE IP Block Memory Generator v6.1

12 www.xilinx.com DS512 March 1, 2011

Product Specification

accepting the Read burst data (by negating RREADY), the Read FSM handles this by holding the data

pipeline until RREADY is asserted.

AXI4 Wrap Burst Support

Cache line operations are implemented as WRAP burst types on AXI when presented to the block

RAM. The allowable burst sizes for WRAP bursts are 2, 4, 8, and 16. The AWBURST/ARBURST must be

set to “10” for the WRAP burst type.

WRAP bursts are handled by the address generator logic of the Write and Read FSM. The address seen

by the block RAM must increment to the address space boundary, and then wrap back around to the

beginning of the cache line address. For example, a processor issues a target word first cache line Read

request to address 0x04h. On a 32-bit block RAM, the address space boundary is 0xFFh. So, the block

X-Ref Target - Figure 12

Figure 12: AXI4 Incremental Read Burst Transactions

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