RAM 7.0 Betriebsanweisung PDF herunterladen (Seite 100)

LogiCORE IP Block Memory Generator v6.1

100 www.xilinx.com DS512 March 1, 2011

Product Specification

Virtex-5 FPGA: Memory with Primitive Output Registers

When Register Port [A|B] Output of Memory Primitives is selected, a memory core that registers the

output of the block RAM primitives for the selected port(s) is generated. In Virtex-5 devices, these

registers are always implemented using the output registers embedded in the Virtex-5 FPGA block

RAM architecture. The output of any multiplexing that may be required to combine multiple primitives

is not registered in this configuration, as shown in Figure 67.

Port A or Port B

 Register Port A Output of Memory Primitives  Register Port B Output of Memory Primitives

 Register Port A Output of Memory Core  Register Port B Output of Memory Core

X-Ref Target - Figure 67

Figure 67: Virtex-5 FPGA Block Memory Generated with Register Port [A|B]

Output of Memory Primitives Enabled

Block Memory Generator Core

Latches

FALSE

Block RAM Primitives

Block RAM

Embedded

Output Registers

Latches

SSR*

Block RAM

Embedded

Output Registers

Latches

SSR*

Block RAM

Embedded

Output Registers

Latches

Use REGCE Pin

REGCE

MUX

CLK

RST

DOUT

R* : The reset (R) of the flop is gated by EN for Spartan-3A DSP, and by CE for Spartan-6

TRUE

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RAM 7.0 Betriebsanweisung Seite 100