
LogiCORE IP Block Memory Generator v6.1
30 www.xilinx.com DS512 March 1, 2011
Product Specification
Byte-Write Example
Consider a Single-port RAM with a data width of 24 bits, or 3 bytes with byte size of 8 bits. The Write
enable bus,
WEA, consists of 3 bits. Figure 31 illustrates the use of byte-writes, and shows the contents
of the RAM at address 0. Assume all memory locations are initialized to 0.
Write First Mode Considerations
When performing a Write operation in WRITE_FIRST mode, the concurrent Read operation shows the
newly written data on the output of the core. However, when using the byte-Write feature in Kintex-7,
Virtex-7, Virtex-6, Virtex-5, Virtex-4, Spartan-6, and Spartan-3A/3A DSP devices or the Read-to-Write
aspect ratio feature in Kintex-7, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 devices, the output of the
memory cannot be guaranteed.
Collision Behavior
The Block Memory Generator core supports Dual-port RAM implementations. Each port is equivalent
and independent, yet they access the same memory space. In such an arrangement, is it possible to have
data collisions. The ramifications of this behavior are described for both asynchronous and
synchronous clocks below.
Collisions and Asynchronous Clocks: General Guidelines
Using asynchronous clocks, when one port writes data to a memory location, the other port must not
Read or Write that location for a specified amount of time. This clock-to-clock setup time is defined in
the device data sheet, along with other block RAM switching characteristics.
Collisions and Synchronous Clocks: General Guidelines
Synchronous clocks cause a number of special case collision scenarios, described below.
• Synchronous Write-Write Collisions. A Write-Write collision occurs if both ports attempt to Write
to the same location in memory. The resulting contents of the memory location are unknown. Note
that Write-Write collisions affect memory content, as opposed to Write-Read collisions which only
affect data output.
X-Ref Target - Figure 31
Figure 31: Byte-Write Example
WEA[2:0]
DINA[23:0]
RAM Contents
CLKA
ADDRA[15:0]
b011
FF EE DD
0000
CC BB AA 33 22 11 00 FF 0099 88 77 66 55 44
b010 b101 b000 b110 b010
00 EE DD 00 BB DD 33 22 77 33 FF 7799 BB 77
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