RAM 7.0 Betriebsanweisung PDF herunterladen (Seite 14)

LogiCORE IP Block Memory Generator v6.1

14 www.xilinx.com DS512 March 1, 2011

Product Specification

Figure 14 illustrates the timing on AXI WRAP or cache line burst Read transactions.

Table 3 provides example address sequence to the block RAM for Wrap transactions.

For more details on AXI4 Wrap Burst Transactions and Wrap boundary calculations, refer to the Burst

Addressing section of the AXI protocol specification [Ref 1].

X-Ref Target - Figure 14

Figure 14: AXI4 Wrap Read Burst Transactions

Table 3: Example Address Sequence for AXI4 BMG Core Wrap Transactions

Memory

Width

Transfer

Size

Start

Address

Burst

Length

AXI4 BMG Core Address Sequence

32-bits 32-bits 0x100Ch 2 0x100Ch

(1)

, 0x1008h

32-bits 32-bits 0x1008h 4 0x1008h, 0x100Ch

(1)

, 0x1000h, 0x1004h

64-bits 64-bits 0x1008h 8

0x1008h, 0x1010h, 0x1018h, 0x1020h, 0x1028h,

0x1030h, 0x1038h

(1)

, 0x1000h

64-bits 16-bits 0x1008h 16

0x1008h, 0x100Ah, 0x100Ch, 0x100Eh, 0x1010,

0x1012, 0x1014, 0x1016h, 0x1018h, 0x101Ah,

0x101Ch, 0x101Eh

(1)

, 0x1000h, 0x1002h, 0x1004h,

0x1006h

1. Calculated Wrap Boundary address.

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