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Product Specification

LogiCORE IP Block Memory Generator v6.1

11 1

“CE”,

“SR”

“SYNC”,

“ASYNC”

Both memory latch and

embedded output register of

primitive are reset. Reset occurs

synchronously or

asynchronously depending on

the Reset Type option, and is

dependent or independent of the

input enable signal based upon

the Reset Priority. Reset value is

asserted for at least two clock

cycles when enable inputs of

both stages are ‘1’, and may be

more depending on the input

RST and enable signals. If RST

is asserted when the latch EN

input is ‘1’ and the register

enable input is ‘0’, the memory

latch alone gets reset and this

reset value gets output only

when the register enable goes

high.

For Kintex-7, Virtex-7, and

Virtex-6 devices, the priority

cannot be set for the latch.

Therefore reset priority of "SR" is

not supported. Both memory

latch and embedded output

register of primitive are reset.

Reset occurs synchronously at

both these stages, and is

dependent or independent of the

input enable signal. Reset value

is asserted for at least two clock

cycles when enable inputs of

both stages are ‘1’, and may be

more depending on the input

RST and enable signals. If RST

is asserted when the latch EN

input is ‘1’ and the register

enable input is ‘0’, the memory

latch alone gets reset and this

reset value gets output only

when the register enable goes

high.

11 0 “SR”

“SYNC”,

“ASYNC”

Fabric register used. Reset

occurs synchronously or

asynchronously when the RST

input is ‘1’, irrespective of the

state of the enable input.

However, the reset value will get

deasserted synchronously only

once the enable input is ‘1’.

Not applicable.

11 1 “SR”

“SYNC”,

“ASYNC”

Reset occurs synchronously or

asynchronously when the RST

input is ‘1’, irrespective of the

state of the enable input.

However, the reset value will get

deasserted synchronously when

the latch and embedded register

are enabled sequentially for at

least one clock cycle each after

the reset input is deasserted.

Not applicable.

1X X

“SR”,

“CE”

ASYNC

Reset occurs asynchronously

when the RST input is ‘1’.

Dependencies on the remaining

options are as explained above.

Not applicable.

Table 8: Control of Reset Behavior in Kintex-7, Virtex-7, Virtex-6, and Spartan-6 for Single Port

Use RSTA Pin

Register Port A Output of

Memory Primitives

Reset Memory Latch

Reset Priority for Port A

Reset Type (Spartan-6 Only)

S6 RESET BEHAVIOR V6 RESET BEHAVIOR

1 2 ... 38 39 40 41 42 43 44 45 46 47 48 ... 117 118

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