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DS512 March 1, 2011 www.xilinx.com 83
Product Specification
LogiCORE IP Block Memory Generator v6.1
AXI4 Block Memory Generator Resource Utilization and Performance
Examples
Table 37 through Table 40 show the resource utilization and performance data for a BMG core using the
AXI4 interface. Benchmarks were taken using a design targeting a Virtex-6 FPGA in the -2 speed grade
(XC6VCX75T-FF484-2) and a Spartan-6 FPGA in the -2 speed grade (XC6SLX150T-FGG484-2). Better
performance may be possible with higher speed grades.
In the benchmark designs, the core was encased in a wrapper with input and output
registers to remove the effects of I/O delays from the results. Performance may vary depending on the
design.
Table 37: AXI4 Block Memory Generator Virtex-6 FPGA
Memory
Type
Options
Width
X
Depth
Resource Utilization
Performance
(MHz)
Block RAMs
FFs LUTs
Occupied
Slices
36K 16K 8K
Simple
Dual Port
RAM
Memory
Slave
32x1024 1 0 0 92 207 74 306
64x512 1 0 0 95 225 81 282
Peripheral
Slave
32x1024 1 0 0 52 151 53 320
64x512 1 0 0 50 145 46 299
Table 38: AXI4 Interface Block Memory Generator Spartan-6 FPGA
Memory
Type
Options
Width
X
Depth
Resource Utilization
Performance
(MHz)
Block RAMs
FFs LUTs
Occupied
Slices
36K 16K 8K
Simple
Dual Port
RAM
Memory
Slave
32x1024 - 2 0 95 207 79 163
64x512 - 2 0 98 231 81 168
Peripheral
Slave
32x1024 - 2 0 56 159 57 175
64x512 - 2 0 54 149 51 165
Table 39: AXI4-Lite Block Memory Generator Virtex-6 FPGA
Memory
Type
Options
Width
X
Depth
Resource Utilization
Performance
(MHz)
Block RAMs
FFs LUTs
Occupied
Slices
36K 16K 8K
Simple
Dual Port
RAM
Memory
Slave
32x1024 1 0 0 15 33 15 325
64x512 1 0 0 15 32 14 317
Peripheral
Slave
32x1024 1 0 0 15 33 15 335
64x512 1 0 0 15 32 14 317
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