RAM 7.0 Betriebsanweisung PDF herunterladen (Seite 102)

LogiCORE IP Block Memory Generator v6.1

102 www.xilinx.com DS512 March 1, 2011

Product Specification

Virtex-4 FPGA: Memory with Primitive Output Registers with RST

If either

Use RSTA Pin (set/reset pin) or Use RSTB Pin (set/reset pin) is selected from the Output Reset

section of the Port Options screen(s)

, the Virtex-4 embedded block RAM registers cannot be used for the

corresponding port(s). The primitive output registers are built from FPGA fabric, as shown in

Figure 69.

Port A or Port B

 Register A Output of Memory Primitives  Register B Output of Memory Primitives

 Register A Output of Memory Core  Register B Output of Memory Core



Use RSTA Pin (set/reset pin)



Use RSTB Pin (set/reset pin)

X-Ref Target - Figure 69

Figure 69: Virtex-4 Block Memory Generated with Register Output of Memory Primitives

and Use RST[A|B] Pin Options Enabled

Block Memory Generator Core

Latches

FALSE

Block RAM Primitives

Block RAM

Embedded

Output Registers

N/A

Latches

SSR*

Block RAM

Embedded

Output Registers

N/A

Latches

SSR*

Block RAM

Embedded

Output Registers

N/A

Latches

Use REGCE Pin

REGCE

CLK

RST

R* : The reset (R) of the flop is gated by CE

TRUE

Primitive

Output Registers

MUX

DOUT

1 2 ... 97 98 99 100 101 102 103 104 105 106 107 ... 117 118

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