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Product Specification

LogiCORE IP Block Memory Generator v6.1

Support

Xilinx provides technical support for this LogiCORE product when used as described in the product

documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in

devices that are not defined in the documentation, if customized beyond that allowed in the product

documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.

Ordering Information

This Xilinx LogiCORE IP module is included at no additional charge with the Xilinx ISE® Design Suite

and is provided under the terms of the Xilinx End User License Agreement

. The core is generated using

the ISE Design Suite CORE Generator software.

For more information, please visit the Block Memory Generator product page

Information about additional LogiCORE IP modules can be found on the Xilinx.com Intellectual

Property page. Contact your local Xilinx sales representative for pricing and availability.

Revision History

The following table shows the revision history for this document:

Date Version Description of Revisions

1/11/06 1.0 Initial Xilinx release

4/12/06 2.0 Updated for Virtex-5 support

7/13/06 3.0

Updated primitives information in Table 1, replaced GUI screens, ISE version,

release date.

9/21/06 4.0 Minor updates for v2.2 release

11/15/06 4.5 Updated for the v2.3 release

2/15/07 5.0 Updated for v2.4 release, added support for ECC.

4/02/07 5.5 Added support for Spartan-3A DSP devices.

8/08/07 6.0 Updated core to v2.5; Xilinx tools v9.2i.

10/10/07 6.5 Updated core to v2.6.

3/24/08 7.0 Updated core to version 2.7; ISE tools 10.1.

9/19/08 8.0 Updated core to version 2.8.

12/17/08 8.0.1 Early access documentation.

4/24/09 9.0 Updated core to version 3.1 and Xilinx tools to version 11.1.

6/24/09 10.0 Updated core to version 3.2 and Xilinx tools to version 11.2.

6/24/09 10.1

Updated Native Block Memory Generator Resource Utilization and

Performance Examples, page 77.

9/16/09 11.0 Updated core to version 3.3 and Xilinx tools to version 11.3.

4/19/10 12.0 Updated to core version 4.1 and ISE 12.1.

7/23/10 13.0 Updated to core version 4.2 and ISE 12.2.

9/21/10 14.0 Updated to core version 4.3 and ISE 12.3.

3/1/11 15.0

Updated to core version 6.1 and ISE 13.1. Added support for AXI4 and AXI4-

Lite interfaces.

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