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Product Specification

LogiCORE IP Block Memory Generator v6.1

• In Kintex-7, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 FPGA-based memories, the Read width may

differ from the Write width by a factor of 1, 2, 4, 8, 16, or 32 for each port. The maximum ratio

between any two of the data widths (

DINA, DOUTA, DINB, and DOUTB) is 32:1.

Optional Byte-Write Enable

In Kintex-7, Virtex-7, Virtex-6, Virtex-5, Virtex-4, Spartan-6, and Spartan-3A/3A DSP FPGA-based

memories, the Block Memory Generator core provides byte-Write support for memory widths which

are multiples of eight (no parity) or nine bits (with parity).

Optional Output Registers

The Block Memory Generator provides two optional stages of output registering to increase memory

performance. The output registers can be chosen for port A and port B separately. The core supports the

Kintex-7, Virtex-7, Virtex-6, Virtex-5, Virtex-4, Spartan-6, and Spartan-3A DSP embedded block RAM

registers as well as registers implemented in the FPGA fabric. See Output Register Configurations,

page 96 for more information about using these registers.

Optional Pipeline Stages

The core provides optional pipeline stages within the MUX, available only when the registers at the

output of the memory core are enabled and only for specific configurations. For the available

configurations, the number of pipeline stages can be 1, 2, or 3. For detailed information, see Optional

Pipeline Stages, page 34.

Optional Enable Pin

The core provides optional port enable pins (ENA and ENB) to control the operation of the memory.

When deasserted, no Read, Write, or reset operations are performed on the respective port. If the enable

pins are not used, it is assumed that the port is always enabled.

Optional Set/Reset Pin

The core provides optional set/reset pins (RSTA and RSTB) for each port that initialize the Read

output to a programmable value.

Memory Initialization

The memory contents can be optionally initialized using a memory coefficient (COE) file or by using the

default data option. A COE file can define the initial contents of each individual memory location, while

the default data option defines the initial content of all locations.

Hamming Error Correction Capability

Simple Dual-port RAM memories support the built-in FPGA Hamming Error Correction Capability

(ECC) available in the Kintex-7, Virtex-7, Virtex-6 and Virtex-5 FPGA block RAM primitives for data

widths greater than 64 bits. The BuiltIn_ECC (ECC) memory automatically detects single- and double-

bit errors, and is able to auto-correct the single-bit errors.

For data widths of 64 bits or less, a soft Hamming Error Correction implementation is available for

Kintex-7, Virtex-7, Virtex-6, and Spartan-6 designs.

Simulation Models

The Block Memory Generator core provides behavioral and structural simulation models in VHDL and

Verilog for both simple and precise modeling of memory behaviors, for example, debugging, probing

the contents of the memory, and collision detection.

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