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DS512 March 1, 2011 www.xilinx.com 17

Product Specification

LogiCORE IP Block Memory Generator v6.1

something other than 0x0h, 0x4h, 0x8h, etc. The example shown in Figure 17 illustrates an unaligned

word burst transaction of 4 data beats, which starts at address offset, 0x1002h.

For more details on AXI4 Narrow Transactions refer to the “about unaligned transfers” section of the

AXI protocol specification [Ref 1].

Configurable Width and Depth

Table 4 provides supported Width and Depth for AXI4 Block Memory core.

For Peripheral Slave configurations, there is no minimum requirement for the number of address bits

used by Block Memory core. For Memory Slave configuration, AXI4 Block Memory slave has at least

sufficient address bits to fully decode a 4kB address range.

For Peripheral Slave and AXI4 Lite Memory Slave configurations, AXI4 Block Memory core is not

required to have low-order address bits to support decoding within the width of the system data bus

and assumes that such low-order address bits have a default value of all zeros. For AXI4 Memory Slave

configuration, AXI4 Block Memory core supports Narrow Transactions and performs low-order

address bits decoding. For more details, see AXI4 Interface Block Memory Addressing, page 17.

AXI4 Interface Block Memory Addressing

AXI4 Interface Block Memory cores support 32-bit byte addressing. There is no minimum requirement

for the number of address bits supplied by a master. Typically a master is expected to supply 32-bits of

X-Ref Target - Figure 17

Figure 17: AXI4 Unaligned Transactions

Table 4: Supported Width and Depth

Operating

Mode

Supported Memory

Data Widths

Supported Minimum

Memory Depth

AXI4 Memory Slave 32,64,128, 256

Supports minimum 4kB address range:

Data Width Minimum Depth

32 1024

64 512

128 256

256 128

AXI4 Lite Memory Slave 32,64

Supports minimum 4kB address range:

Data Width

Minimum Depth

32 1024

64 512

AXI4 Peripheral Slave 8, 16, 32,64,128, 256 2

AXI4 Lite Peripheral Slave 8, 16, 32,64, 2

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