RAM 7.0 Betriebsanweisung PDF herunterladen (Seite 10)

LogiCORE IP Block Memory Generator v6.1

10 www.xilinx.com DS512 March 1, 2011

Product Specification

Figure 9 illustrates single burst Read operations to block RAM. The registered ARREADY signal output

on the AXI Read Address Channel interface defaults to a high assertion. The AXI Read FSM can accept

the read address in the clock cycle where the ARVALID signal is first valid.

The AXI Read FSM can accept a same clock cycle assertion of the RREADY by the master if the master

can accept data immediately. When the RREADY signal is asserted on the AXI bus by the master, the

Read FSM will either negate the RVALID signal or will place next valid data on the AXI Bus.

For more details on AXI4 Channel handshake sequences refer to the “Channel Handshake” section of

the AXI protocol specification [Ref 1].

AXI4 Lite Single Burst Transactions

For AXI4 Lite interfaces, all transactions are burst length of one and all data accesses are the same size

as the width of the data bus. Figure 9 and Figure 10 illustrates timing of AXI 32-bit write operations to

the 32-bit wide BRAM. Figure 9 example illustrates single burst Write operations to block RAM

addresses 0x1000h and 0x1004h. Figure 10 illustrates single burst Read operations to block RAM

addresses 0x1000h and 0x1004h.

AXI4 Incremental Burst Support

Figure 11 illustrates an example of the timing for an AXI Write burst of four words to a 32-bit block

RAM. The address Write channel handshaking stage communicates the burst type as INCR, the burst

length of two data transfers (AWLEN = 01h). The Write burst utilizes all byte lanes of the AXI data bus

going to the block RAM (AWSIZE = 010b).

X-Ref Target - Figure 10

Figure 10: AXI4 Lite Single Burst Read Transactions

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RAM 7.0 Betriebsanweisung Seite 10