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DS512 March 1, 2011 www.xilinx.com 93

Product Specification

LogiCORE IP Block Memory Generator v6.1

20 C_HAS_MEM_OUTPUT_REGS_A Integer 0

Determines whether port A has a

the memory latch.

21 C_HAS_MEM_OUTPUT_REGS_B Integer 0

Determines whether port B has a

the memory latch.

22 C_HAS_MUX_OUTPUT_REGS_A Integer 0

Determines whether port A has a

the memory core.

23 C_HAS_MUX_OUTPUT_REGS_B Integer 0

Determines whether port B has a

the memory core.

24 C_MUX_PIPELINE_STAGES Integer 0

Determines the number of pipeline

stages within the MUX for both port

A and port B.

25 C_WRITE_WIDTH_A Integer 8 to 256 Defines width of Write port A.

26 C_READ_WIDTH_A Integer 8 to 256 Defines width of Read port A.

27 C_WRITE_DEPTH_A Integer 2 to 9011200 Defines depth of Write port A.

28 C_READ_DEPTH_A Integer 2 to 9011200 Defines depth of Read port A.

29 C_ADDRA_WIDTH Integer 1 to 32 Defines the width of address A.

30 C_WRITE_MODE_A String Write_First, Read_first Defines the Write mode for port A.

31 C_HAS_ENA Integer 1

Determines whether port A has an

enable pin.

32 C_HAS_REGCEA Integer 0

Determines whether port A has an

enable pin for its output register.

33 C_HAS_RSTA Integer 0

Determines whether port A has

reset pin.

34 C_INITA_VAL String 0

Defines initialization/power-on value

for port A output.

35 C_USE_BYTE_WEA Integer 0, 1

Determines whether byte-Write

feature is used on port A.

For True Dual Port configurations,

this value is the same as

C_USE_BYTE_WEB, since there is

only a single byte Write enable

option provided.

36 C_WEA_WIDTH Integer 1 to 128 Defines width of WEA pin for port A.

37 C_WRITE_WIDTH_B Integer 8 to 256 Defines width of Write port B.

38 C_READ_WIDTH_B Integer 8 to 256 Defines width of Read port B.

39 C_WRITE_DEPTH_B Integer 2 to 9011200 Defines depth of Write port B.

40 C_READ_DEPTH_B Integer 2 to 9011200 Defines depth of Read port B.

41 C_ADDRB_WIDTH Integer 1 to 32 Defines the width of address B.

42 C_WRITE_MODE_B String

Write_First,

Read_first,

Defines the Write mode for port B.

43 C_HAS_ENB Integer 1

Determines whether port B has an

enable pin.

Table 44: AXI4 Interface SIM Parameters (Cont’d)

SIM Parameter Type Values Description

1 2 ... 88 89 90 91 92 93 94 95 96 97 98 ... 117 118

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