RAM 7.0 Betriebsanweisung PDF herunterladen (Seite 7)

DS512 March 1, 2011 www.xilinx.com 7

Product Specification

LogiCORE IP Block Memory Generator v6.1

All Write operations are initiated on the Write Address Channel (AW) of the AXI bus. The AW channel

specifies the type of Write transaction and the corresponding address information. The Write Data

Channel (W) communicates all Write data for single or burst Write operations. The Write Response

Channel (B) is used as the handshaking or response to the Write operation.

On Read operations, the Read Address Channel (AR) communicates all address and control

information when the AXI master requests a Read transfer. When the Read data is available to send

back to the AXI master, the Read Data Channel (R) transfers the data and status of the Read operation

Applications

AXI4 Block Memories - Memory Slave Mode

AXI4 Block Memories in Memory Slave mode are optimized for Memory Mapped System Bus

implementations. The AXI4 Memory Slave Interface Type supports aligned, unaligned or narrow

transfers for incremental or wrap bursts.

Figure 3 shows an example application for the AXI4 Memory Slave Interface Type with an AXI4

Interconnect for Multi Master AXI4 applications. Minimum memory requirement for this configuration

is set to 4K bytes. Data widths supported by this configuration include 32, 64, 128 or 256 bits

AXI4-Lite Block Memories - Memory Slave Mode

AXI4-Lite Block Memories in Memory Slave mode are optimized for the AXI4-Lite interface. They can

be used in implementations requiring simple Control/Status Accesses. AXI4-Lite Memory Slave

Interface Type supports only single burst transactions.

X-Ref Target - Figure 3

Figure 3: AXI4 Memory Slave Application Diagram

X-Ref Target - Figure 4

Figure 4: AXI4-Lite Memory Slave Application Diagram

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RAM 7.0 Betriebsanweisung Seite 7