RAM 7.0 Betriebsanweisung PDF herunterladen (Seite 40)

LogiCORE IP Block Memory Generator v6.1

40 www.xilinx.com DS512 March 1, 2011

Product Specification

The special reset behavior of Spartan-3A DSP devices also differs from standard reset behavior in that

the reset of the latch and embedded output register is gated by the EN input to the core, independent of

the state of REGCE. As shown in Figure 43, the enable input is low during the first reset, and therefore

the reset value is not asserted at the output. However during the second reset, the ENA input is high,

and the reset value is asserted at the output for two clock cycles.

In Kintex-7, Virtex-7, Virtex-6, and Spartan-6 devices, the reset of the memory latch is gated by EN, and

the reset of the embedded register is gated by CE, similar to other architectures. As shown in Figure 44,

both ENA and REGCEA are high at the time of the first reset, and the reset value is asserted at the output

for two clock cycles. At the time of the second reset, ENA is high, but REGCEA is low; so the reset value

X-Ref Target - Figure 41

Figure 41: Standard Reset Behavior Similar to Previous Architectures

X-Ref Target - Figure 42

Figure 42: Special Reset Behavior using the Reset Memory Latch Option

X-Ref Target - Figure 43

Figure 43: Reset Gated by EN in Spartan-3A DSP Devices with the Reset Memory Latch Option

CLKA

aa bb cc

0000 MEM(bb)

ENA

RSTA

ADDRA

DOUTA[15:0]

Operation

ReadReadReset

INIT_VAL

MEM(cc)

CLKA

aa bb cc

0000 INIT_VAL

ENA

RSTA

ADDRA

DOUTA[15:0]

Operation

Reset ReadReset

MEM(cc)

DOUTA[15:0]

CLKA

ADDRA

ENA

INIT_VAL

0000

OPERATION

READ

RESET

READ

cc dd

RSTA

REGCE

MEM(aa)

RESET

OPERATION

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