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LogiCORE IP Block Memory Generator v6.1

44 www.xilinx.com DS512 March 1, 2011

Product Specification

Built-in Error Correction Capability and Error Injection

For Kintex-7, Virtex-7, Virtex-6, and Virtex-5 devices, the Block Memory Generator core supports built-

in Hamming Error Correction Capability (ECC) for the block RAM primitives. For device support, see

Table 9. Each Write operation generates eight protection bits for every 64 bits of data, which are stored

with the data in memory. These bits are used during each Read operation to correct any single-bit error,

or to detect (but not correct) any double-bit error.

This operation is transparent to the user. Two status outputs (SBITERR and DBITERR) indicate the

three possible Read results: no error, single error corrected, and double error detected. For single-bit

errors, the Read operation does not correct the error in the memory array; it only presents corrected

data on DOUT. BuiltIn_ECC is only available when the following options are chosen:

• Kintex-7, Virtex-7, Virtex-6, and Virtex-5 FPGAs

• Simple Dual-port RAM memory type

When using BuiltIn_ECC, the Block Memory Generator constructs the memory from special primitives

available in Kintex-7, Virtex-7, Virtex-6, and Virtex-5 FPGA architectures. The BuiltIn_ECC memory

block is 512x64, and is composed of two 18k block RAMs combined with dedicated BuiltIn_ECC

encoding and decoding hardware. The 512x64 primitives are used to build memory sufficient for the

desired user memory space.

The Kintex-7, Virtex-7, Virtex-6, and Virtex-5 BuiltIn_ECC primitives calculate BuiltIn_ECC for a 64-bit

wide data input. If the data width chosen by a user is not an integral multiple of 64 (for example, there

are spare bits in any BuiltIn_ECC primitive), then a double-bit error (DBITERR) may indicate that one

or more errors have occurred in the spare bits. So, the accuracy of the DBITERR signal cannot be

guaranteed in this case. For example, if the user's data width is 32, then 32 bits of the primitive are left

spare. If two of the spare bits are corrupted, the DBITERR signal would be asserted even though the

actual user data is not corrupt.

When using BuiltIn_ECC, the following limitations apply:

• Byte-Write enable is not available

• All port widths must be identical

• For Virtex-5 devices, No Change Operating mode is supported, and for Kintex-7, Virtex-7, Virtex-

6, and Virtex-5 devices, Read First Operating Mode is supported

• Use RST[A|B] Pin and the Output Reset Value options are not available

• Memory Initialization is not supported

• No Algorithm selection is available

Table 9: Hard ECC Data width Support

Kintex-7 Virtex-7 Virtex-6 Virtex-5 Spartan-6

Block RAM Mode SDP Mode +

Read First

SDP Mode +

Read First

SDP Mode +

Read First

SDP Mode + No

Change

n/a

Supported Data

Widths

 64  64  64  64 n/a

Bit Error Insertion

Support

Ye s Ye s Ye s N o n / a

1 2 ... 39 40 41 42 43 44 45 46 47 48 49 ... 117 118

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