RAM 7.0 Betriebsanweisung PDF herunterladen (Seite 13)

DS512 March 1, 2011 www.xilinx.com 13

Product Specification

LogiCORE IP Block Memory Generator v6.1

RAM will see the following sequence of addresses for Read requests: 0x04h, 0x08h, 0x0Ch, 0x00h. Note

the wrap of the cache line address from 0xCh back to 0x00h at the end.

Figure 13 illustrates the timing for AXI Wrap or cache line burst transactions. The address generated

and presented to the block RAM starts at the target word and wraps around once the address space

boundary is reached.

X-Ref Target - Figure 13

Figure 13: AXI4 Wrap Write Burst Transactions

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RAM 7.0 Betriebsanweisung Seite 13