RAM 7.0 Betriebsanweisung PDF herunterladen (Seite 114)

LogiCORE IP Block Memory Generator v6.1

114 www.xilinx.com DS512 March 1, 2011

Product Specification

Spartan-3 FPGA: Memory with Primitive Output Registers

When Register Port [A|B] Output of Memory Primitives is selected, a core that only registers the

output of the RAM primitives is generated. Note that the output of any multiplexing required to

combine multiple primitives are not registered in this configuration, as shown in Figure 79.

Port A or Port B

 Register Port A Output of Memory Primitives  Register Port B Output of Memory Primitives

 Register Port A Output of Memory Core  Register Port B Output of Memory Core

X-Ref Target - Figure 79

Figure 79: Spartan-3 Block Memory Generated with Register Port [A|B]

Output of Memory Primitives Enabled

Block Memory Generator Core

Latches

REGCE

Primitive

Output

Registers

MUX

Block RAM Primitives

Block RAM

CLK

RST

DOUT

S* : The synchronous reset (S) of the flop is gated by CE

Block RAM

Latches

FALSE

Use REGCE Pin

TRUE

1 2 ... 109 110 111 112 113 114 115 116 117 118

Keine Kommentare

RAM 7.0 Betriebsanweisung Seite 114