RAM 7.0 Betriebsanweisung PDF herunterladen (Seite 22)

LogiCORE IP Block Memory Generator v6.1

22 www.xilinx.com DS512 March 1, 2011

Product Specification

Selectable Memory Algorithm

The Block Memory Generator core arranges block RAM primitives according to one of three

algorithms: the minimum area algorithm, the low power algorithm and the fixed primitive algorithm.

Minimum Area Algorithm

The minimum area algorithm provides a highly optimized solution, resulting in a minimum number of

block RAM primitives used, while reducing output multiplexing. Figure 23 shows two examples of

memories built using the minimum area algorithm.

Note:

In Spartan-6 devices, two 9K block RAMs are used for one 1Kx18.

In the first example, a 3kx16 memory is implemented using three block RAMs. While it may have been

possible to concatenate three 1kx18 block RAMs in depth, this would require more output

multiplexing. The minimum area algorithm maximizes performance in this way while maintaining

minimum block RAM usage.

In the second example, a 5kx17 memory, further demonstrates how the algorithm can pack block RAMs

efficiently to use the fewest resources while maximizing performance by reducing output multiplexing.

Low Power Algorithm

The low power algorithm provides a solution that minimizes the number of primitives enabled during

a Read or Write operation. This algorithm is not optimized for area and may use more block RAMs and

X-Ref Target - Figure 23

Figure 23: Examples of the Minimum Area Algorithm

3kx16 memory

2kx9

1kx18

2kx9

5kx17 memory

4kx4 4kx4

2kx9

1kx18

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RAM 7.0 Betriebsanweisung Seite 22