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LogiCORE IP Block Memory Generator v6.1

18 www.xilinx.com DS512 March 1, 2011

Product Specification

addressing. Table 5 illustrates some example settings to create a specific size of block RAM in the

system.

The Address Range of AXI Block Memory core must always start at zero. If the master has a different

address bus width than that provided by the AXI4 Block Memory Core, follow these guidelines:

• If the Master address is wider than the configured Address Range for AXI Block Memory core, the

additional high-order address bits can be connected as is. AXI Block Memory core will ignore

these bits.

• If the Master address is narrower than 32-bits, the high-order address bits of the AXI Block

Memory core can be left unconnected.

For more details on AXI4 Addressing refer to the “Master Addresses” and “Slave Addresses” section of

the AXI protocol specification [Ref 1].

Throughput & Performance

To achieve 100 percent block RAM interface utilization of the Write port the following conditions must

be satisfied.

• No single Write bursts.

• The AXI Master should not apply back pressure on the Write response channel

To achieve 100 percent block RAM interface utilization of the Read port the following conditions must

be satisfied.

• The AXI Master should not apply back pressure on the Read data channel

Selectable Port Aspect Ratios

The core currently supports only symmetric aspect ratios (that is, a 1:1 aspect ratio only).

Optional Output Register

The Output Register option is currently not supported.

Table 5: AXI4 Interface Block Memory Generator Example Address Ranges

Memory

Width x Depth

Memory

Size

Address Range

Required

Example

Base Address

Example

Max Address

Block RAM

Address

8 x 4096 4K

0x0000_0000

to 0x0000_0FFF

0xA000 0000 0xA000 0FFF AXI_ADDR[11:0]

16 x 2048 4K

0x0000_0000

to 0x0000_0FFF

0xA000 0000 0xA000 0FFF AXI_ADDR[11:1]

32 x 1024 4K

0x0000_0000

to 0x0000_0FFF

0xA000 0000 0xA000 0FFF AXI_ADDR[11:2]

64 x 1024 8K

0x0000_0000

to 0x0000_1FFF

0x2400 0000 0x2400 1FFF AXI_ADDR[12:3]

128 x 1024 16K

0x0000_0000

to 0x0000_3FFF

0x1F00 0000 0x1F00 3FFF AXI_ADDR[13:4]

256 x 1024 32K

0x0000_0000

to 0x0000_7FFF

0x3000 0000 0x3000 7FFF AXI_ADDR[14:5]

1 2 ... 13 14 15 16 17 18 19 20 21 22 23 ... 117 118

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