RAM 7.0 Betriebsanweisung PDF herunterladen (Seite 68)

LogiCORE IP Block Memory Generator v6.1

68 www.xilinx.com DS512 March 1, 2011

Product Specification

Output Registers and Memory Initialization Screen

Optional Output Registers

Select the output register stages to include:

• Register Port [A|B] Output of Memory Primitives. Select to insert output register after the

memory primitives for port A and port B separately. When targeting Kintex-7, Virtex-7, Virtex-6,

Virtex-5 or Virtex-4 FPGAs, the embedded output registers in the block RAM primitives are used

if the user chooses to register the output of the memory primitives. For Spartan-6 and Spartan-3A

DSP, either the primitive embedded registers or fabric registers from FPGA slices are used,

depending upon the Reset Behavior option chosen by the user. For other architectures, the

registers in the FPGA slices are used. Note that in Virtex-4 devices, the use of the RST input

prevents the core from using the embedded output registers. See Output Register Configurations,

page 96 for more information.

• Register Port [A|B] Output of Memory Core. Select for each port (A or B) to insert a register on

the output of the memory core for that port. When selected, registers are implemented using

FPGA slices to register the core's output.

• Use REGCE [A|B] Pin. Select to use a separate REGCEA or REGCEB input pin to control the

enable of the last output register stage in the memory. When unselected, all register stages are

enabled by ENA/ENB.

• Pipeline Stages within Mux. Available only when the Register Output of Memory Core option is

selected for both port A and port B and when the constructed memory has more than one

primitive in depth, so that a MUX is needed at the output. Select a value of 0, 1, 2, or 3 from the

drop-down list.

X-Ref Target - Figure 56

Figure 56: Output Registers and Memory Initialization Screen

1 2 ... 63 64 65 66 67 68 69 70 71 72 73 ... 117 118

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RAM 7.0 Betriebsanweisung Seite 68