RAM 7.0 Betriebsanweisung PDF herunterladen (Seite 106)

LogiCORE IP Block Memory Generator v6.1

106 www.xilinx.com DS512 March 1, 2011

Product Specification

Spartan-6 or Spartan-3A DSP FPGA: Memory with Primitive and Core Output Registers

With both Register Port [A|B] Output of Memory Primitives and the corresponding Register Port

[A|B] Output of Memory Core selected, a memory core is generated with both the embedded output

registers and a register on the output of the core for the selected port(s), as shown in Figure 72. This

configuration may improve performance when building a large memory construct.

Port A or Port B

 Register Port A Output of Memory Primitives  Register Port B Output of Memory Primitives

 Register Port A Output of Memory Core  Register Port B Output of Memory Core

X-Ref Target - Figure 72

Figure 72: Spartan-6 or Spartan-3A DSP Block Memory Generated with Register Port [A|B]

Output of Memory Primitives and Register Port [A|B] Output of Memory Core Enabled

Block Memory Generator Core

Core

Output

Registers

Latches

FALSE

Block RAM Primitives

Block RAM

Embedded

Output Registers

Latches

SSR*

Block RAM

Embedded

Output Registers

Latches

SSR*

Block RAM

Embedded

Output Registers

Latches

Use REGCE Pin

REGCE

MUX

CLK

RST

DOUT

R* : The reset (R) of the flop is gated by CE

TRUE

1 2 ... 101 102 103 104 105 106 107 108 109 110 111 ... 117 118

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