RAM 7.0 Betriebsanweisung PDF herunterladen (Seite 11)

DS512 March 1, 2011 www.xilinx.com 11

Product Specification

LogiCORE IP Block Memory Generator v6.1

In compliance with AXI Protocol, the burst termination boundary for a transaction is determined by the

length specified in the AWLEN signal. The allowable burst sizes for INCR bursts are from 1 (00h) to 256

(FFh) data transfers.

Figure 12 illustrates the example timing for an AXI Read burst with block RAM managed by the Read

FSM. The memory Read burst starts at address 0x1000h of the block RAM. On the AXI Read Data

Channel, the Read FSM enables the AXI master/Interconnect to respond to the RVALID assertion when

RREADY is asserted in the same clock cycle. If the requesting AXI master/Interconnect throttles on

X-Ref Target - Figure 11

Figure 11: AXI4 Incremental Write Burst Transactions

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