RAM 7.0 Betriebsanweisung PDF herunterladen (Seite 110)

LogiCORE IP Block Memory Generator v6.1

110 www.xilinx.com DS512 March 1, 2011

Product Specification

Port A or Port B

 Register Port A Output of Memory Primitives  Register Port B Output of Memory Primitives

 Register Port A Output of Memory Core  Register Port B Output of Memory Core



Use RSTA Pin (set/reset pin)



Use RSTB Pin (set/reset pin)

 Reset Memory Latch  Reset Memory Latch

X-Ref Target - Figure 75

Figure 75: Spartan-6 or Spartan-3A DSP Block Memory Generated with Register Port [A|B]

Gated by EN in Spartan-3A DSP and by CE in Spartan-6 Output of Memory Primitives, Use

RST[A|B] Pin Options (With RST), and Special Reset Behavior Enabled

Block Memory Generator Core

Latches

FALSE

Block RAM Primitives

Block RAM

Embedded

Output Registers

Latches

SSR*

Block RAM

Embedded

Output Registers

Latches

SSR*

Block RAM

Embedded

Output Registers

Latches

Use REGCE Pin

REGCE

MUX

CLK

RST

DOUT

R* : The reset (R) of the flop is gated by EN for Spartan-3A DSP, and by CE for Spartan-6

TRUE

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RAM 7.0 Betriebsanweisung Seite 110