RAM 7.0 Betriebsanweisung PDF herunterladen (Seite 39)

DS512 March 1, 2011 www.xilinx.com 39

Product Specification

LogiCORE IP Block Memory Generator v6.1

Figure 40 illustrates the reset behavior when the Reset Priority option is set to SR. Here, reset is not

dependent on enable and both reset operations occur successfully.

Special Reset Behavior

For Kintex-7, Virtex-7, Virtex-6, Spartan-6, and Spartan-3A DSP devices, the Block Memory Generator

provides the option to reset both the memory latch and the embedded primitive output register. This

Reset Behavior option is available to users when they choose to have a primitive output register, but no

core output register. When a user chooses the option to Reset the Memory Latch besides the primitive

output register, then the reset value is asserted at the output for two clock cycles. However, when the

user does not choose the option to Reset the Memory Latch in the presence of a primitive output

Note that the duration of reset assertion specified here is the minimum duration when the latch and

are de-asserted or the RST input is held high for more than one clock cycle, the reset value may be

asserted at the output for a longer duration.

In Kintex-7, Virtex-7, and Virtex-6 devices, the latch and the embedded output register can be reset

independently using two separate inputs (RSTREG and RSTRAM) that are connected to the primitive.

So, if the user does not choose to reset the memory latch, only the embedded output register is reset.

In Spartan-6 and Spartan-3A DSP, the same reset signal (RST) is connected to both the latch and the

embedded output register. So, if the user does not choose to reset the memory latch, the primitive

output register needs to be constructed out of fabric to get the desired behavior. Thus in Spartan-6 and

Spartan-3A DSP devices, by choosing the option to reset the memory latch, the reset behavior is

modified slightly but resources are saved since the embedded register is used.

Figure 41 and Figure 42 illustrate the difference between the standard reset behavior similar to

previous architectures obtained when the memory latch is not reset, and the special reset behavior in

the new architectures, obtained when the memory latch is reset. Note that there is an extra clock cycle

of latency in the data output because of the presence of the primitive output register.

X-Ref Target - Figure 40

Figure 40: Reset Behavior When Reset Priority is Set to SR

CLKA

aa bb cc dd ee

0000 MEM(aa) INIT_VAL

ENA

RSTA

ADDRA

DOUTA[15:0]

Operation

ReadReset Read Reset

MEM(cc) INIT_VAL

1 2 ... 34 35 36 37 38 39 40 41 42 43 44 ... 117 118

Keine Kommentare

RAM 7.0 Betriebsanweisung Seite 39