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LogiCORE IP Block Memory Generator v6.1
72 www.xilinx.com DS512 March 1, 2011
Product Specification
Power Estimate Options
The Power Estimation tab on the left side of the GUI screen shown in Figure 59 provides a rough
estimate of power consumption for the core based on the configured Read width, Write width, clock
rate, Write rate and enable rate of each port. The power consumption calculation assumes a toggle rate
50%. More accurate estimates can be obtained on the routed design using the XPower Analyzer tool.
See www.xilinx.com/power
for more information on the XPower Analyzer.
The screen has an option to provide "Additional Inputs for Power Estimation" apart from configuration
parameters. The following parameters can be entered by the user for power calculation:
Clock Frequency [A|B]: The operating clock frequency of the two ports A and B respectively.
Write Rate [A|B]: Write rate of ports A and B respectively.
Enable Rate [A|B]: Average access rate of port A and B respectively.
Structural/UNISIM Simulation Model Options
Select the type of warning messages and outputs generated by the structural simulation model in the
event of collisions. For the options of ALL, WARNING_ONLY and GENERATE_X_ONLY, the collision
detection feature will be enabled in the UniSim models to handle collision under any condition.
The NONE selection is intended for designs that have no collisions and clocks (Port A and Port B) that
are never in phase or within 3000 ps in skew. If NONE is selected, the collision detection feature will be
disabled in the models, and the behavior during collisions is left for the simulator to handle. So, the
output will be unpredictable if the clocks are in phase or from the same clock source or within 3000 ps
in skew, and the addresses are the same for both ports. The option NONE is intended for design with
clocks never in phase.
X-Ref Target - Figure 59
Figure 59: Power Estimate Options Screen
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