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7 Series FPGAs Memory Resources www.xilinx.com 9
UG473 (v1.11) November 12, 2014
Preface
About This Guide
Xilinx® 7 series FPGAs include three FPGA families that are all designed for lowest power
to enable a common design to scale across families for optimal power, performance, and
cost. The Artix®-7 family is optimized for lowest cost and absolute power for the highest
volume applications. The Virtex®-7 family is optimized for highest system performance
and capacity. The Kintex®-7 family is an innovative class of FPGAs optimized for the best
price-performance. This guide serves as a technical reference describing the 7 series FPGAs
block RAMs. Block RAMs are used for efficient data storage or buffering, for
high-performance state machines or FIFO buffers, for large shift registers, large look-up
tables, or ROMs.
This 7 series FPGAs memory resources user guide, part of an overall set of documentation
on the 7 series FPGAs, is available on the Xilinx website at:
w
ww.xilinx.com/support/documentation/7_series
Guide Contents
This manual contains these chapters:
• Chapter 1, Block RAM Resources
• Chapter 2, Built-in FIFO Support
• Chapter 3, Built-in Error Correction
7 Series FPGAs Block RAM and FIFO Differences from Previous
FPGA Generations
Changes from Virtex-6 FPGAs
• The rules for conflict avoidance and address collision are relaxed.
• In SDP mode, the WRITE_FIRST mode is automatically mapped to the NO_CHANGE
mode for power savings.
• The block RAM content initialization and readback behavior is changed due to a new
power gating implementation.
• The new external power supply V
CCBRAM
is used to power the block RAM memory
cells.
• The FIFO reset requirements are simplified in 7 series FPGAs. The FIFO reset
assertion is now synchronized to the read and write clocks. However, the reset
deassertion is still asynchronous.
• Overall, the FIFO flag latencies are different than in Virtex-6 FPGAs (see Table 2-4).
- 7 Series FPGAs 1
- Memory Resources 1
- Revision History 2
- RCCK_RST 3
- RCKC_RST 3
- RREC_RST 3
- RREM_RST 3
- Table of Contents 5
- About This Guide 9
- Additional Support Resources 10
- Block RAM Resources 11
- Block RAM Introduction 13
- UG473_c1_01_052610 15
- Read Operation 16
- Write Operation 16
- Write Modes 16
- NO_CHANGE Mode 17
- Conflict Avoidance 18
- Optional Output Registers 19
- Simple Dual-Port Block RAM 20
- Cascadable Block RAM 21
- Byte-Wide Write Enable 21
- RAMB36E1 TDP mode 36 4 22
- RAMB36E1 SDP mode 72 8 22
- RAMB18E1 TDP mode 18 2 22
- RAMB18E1 SDP mode 36 4 22
- Block RAM Library Primitives 23
- Block RAM Port Signals 26
- Set/Reset 27
- Cascade In 29
- Block RAM Address Mapping 30
- Block RAM Attributes 31
- Read Width - READ_WIDTH_[A 33
- Avoidance, page 18 34
- Considerations 35
- Block RAM Applications 37
- Block RAM 38
- Register 38
- Block RAM Timing Model 39
- RCCK_REGCE 40
- RCKC_REGCE 40
- RCKO_DO_REG 40
- Clock Event 1 41
- Clock Event 2 41
- Clock Event 4 41
- Stacked Silicon Interconnect 43
- Built-in FIFO Support 45
- Synchronous FIFO 46
- FIFO Primitives 48
- UG473_c2_04_052610 49
- Standard Mode 51
- UG473_c2_05_052610 51
- Empty Flag 52
- Almost Empty Flag 52
- Read Error Flag 52
- Full Flag 53
- Write Error Flag 53
- Almost Full Flag 53
- FIFO Timing Characteristics 58
- EMPTY Signal 59
- RCCK_WREN 60
- RCKO_AFULL 60
- RCKO_FULL 60
- RCKO_WRERR 61
- RCCK_RDEN 61
- FIFO Applications 64
- UG473_c2_11_052610 65
- 512 x 144 FIFO 66
- UG473_c2_12_052610 66
- UG473_c2_13_052610 67
- Built-in Error Correction 69
- ECC Modes 70
- UG473_c3_01_052610 71
- RAMB36E1 72
- UG473_c3_03_052610 73
- FIFO36E1 73
- ECC Modes of Operation 76
- UG473_c3_06_100610 78
- UG473_c3_07_070110 78
- Standard ECC 79
- Standard ECC Write 80
- Standard ECC Read 80
- Set by Attributes 80
- ECC Encode-Only Write 80
- ECC Encode-Only Read 81
- DO_REG = 0 82
- DO_REG = 1 82
- Encode-Only ECC Write Timing 83
- Encode-Only ECC Read Timing 83
- Decode-Only ECC Write Timing 83
- Decode-Only ECC Read Timing 83
- RCKO_PARITY_ECC 85
- RCKO_SBIT_ECC 85
- RCKO_SBIT_ECC_REG 85
- RCKO_DBIT_ECC 85
- RCKO_DBIT_ECC_REG 85
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