
78 www.xilinx.com 7 Series FPGAs Memory Resources
UG473 (v1.11) November 12, 2014
Chapter 3: Built-in Error Correction
X-Ref Target - Figure 3-6
Figure 3-6: Single Double-Bit Error Injection in Register Mode
DIN
Write
Cycle
Read
Cycle
WRCLK
WREN
WRADDR
INJSBITERR
INJDBITERR
RDCLK
RDADDR
RDEN
DOUT
SBITERR
DBITERR
ABCD
UG473_c3_06_100610
EF
0123 45
123
ABxC
SBITERR Corrected Data
DBITERR Not Corrected Data
T
RCKO_RDADDR_ECC_REG
T
RCKO_DO_REG
T
RCKO_SBIT_ECC
T
RCKO_DBIT_ECC
T
RDCK_DI_ECC
T
RDCK_INJERR_ECC
X-Ref Target - Figure 3-7
Figure 3-7: Single Double-Bit Error Injection in Latch Mode
DIN
Write
Cycle
Read
Cycle
WRCLK
WREN
WRADDR
INJSBITERR
INJDBITERR
RDCLK
RDADDR
RDEN
DOUT
SBITERR
DBITERR
ABCD
UG473_c3_07_070110
EF
0123 45
123
ABxC
SBITERR Corrected Data
DBITERR Not Corrected Data
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