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7 Series FPGAs Memory Resources www.xilinx.com 11

UG473 (v1.11) November 12, 2014

Chapter 1

Block RAM Resources

Summary

The block RAM in Xilinx® 7 series FPGAs stores up to 36 Kbits of data and can be

configured as either two independent 18 Kb RAMs, or one 36 Kb RAM. Each 36 Kb block

RAM can be configured as a 64K x 1 (when cascaded with an adjacent 36 Kb block RAM),

32K x 1, 16K x 2, 8K x 4, 4K x 9, 2K x 18, 1K x 36, or 512 x 72 in simple dual-port mode.

Each 18 Kb block RAM can be configured as a 16K x 1, 8K x2 , 4K x 4, 2K x 9, 1K x 18 or

512 x 36 in simple dual-port mode.

Similar to the Virtex®-6 FPGA block RAMs, Write and Read are synchronous operations;

the two ports are symmetrical and totally independent, sharing only the stored data. Each

port can be configured in one of the available widths, independent of the other port. In

addition, the read port width can be different from the write port width for each port. The

memory content can be initialized or cleared by the configuration bitstream. During a

write operation the memory can be set to have the data output remain unchanged, reflect

the new data being written or the previous data now being overwritten.

The 7 series FPGAs block RAM features include:

• Per block memory storage capability where each block RAM can store up to 36 Kbits

of data.

• Support of two independent 18Kb blocks, or a single 36Kb block RAM.

• Each 36Kb block RAM can be set to simple dual-port (SDP) mode, doubling data

width of the block RAM to 72 bits. The 18Kb block RAM can also be set to simple

dual-port mode, doubling data width to 36 bits. Simple dual-port mode is defined as

having one read-only port and one write-only port with independent clocks.

• The simple dual-port RAM supports a fixed width data port setting on one side with a

variable data port width setting on the other side.

• Two adjacent block RAMs can be combined to one deeper 64K x 1 memory without

any external logic.

• One 64-bit Error Correction Coding block is provided per 36 Kb block RAM or 36 Kb

FIFO. Separate encode/decode functionality is available. Capability to inject errors in

ECC mode.

• Synchronous Set/Reset of the outputs to an initial value is available for both the latch

and register modes of the block RAM output.

• Separate synchronous Set/Reset pins to independently control the Set/Reset of the

optional output registers and output latch stages in the block RAM.

• An attribute to configure the block RAM as a synchronous FIFO to eliminate flag

latency uncertainty.

• The FULL flag in 7 series FPGAs is asserted without any latency.

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RAM 8.0 BUX II Series Betriebsanweisung Seite 11