RAM 8.0 BUX II Series Betriebsanweisung PDF herunterladen (Seite 64)

64 www.xilinx.com 7 Series FPGAs Memory Resources

UG473 (v1.11) November 12, 2014

Chapter 2: Built-in FIFO Support

Case 5: Resetting All Flags

Figure 2-10 shows the timing when all the flags are reset.

When the reset signal is asserted, all flags are reset.

• At time T

RCO_EMPTY

, after reset (RST), empty is asserted at the EMPTY output pin of

the FIFO.

• At time T

RCO_AEMPTY

, after reset (RST), almost empty is asserted at the AEMPTY

output pin of the FIFO.

• At time T

RCO_FULL

, after reset (RST), full is deasserted at the FULL output pin of the

FIFO.

• At time T

RCO_AFULL

, after reset (RST), almost full is deasserted at the AFULL output

pin of the FIFO.

Reset is an asynchronous signal used to reset all flags. Hold the reset signal High for five

read and write clock cycles to ensure that all internal states and flags are reset to the correct

value.

Case 6: Simultaneous Read and Write for Dual-Clock FIFO

Simultaneous read and write operations for an asynchronous FIFO is not deterministic

when the FIFO is at the condition to assert a status flag. The FIFO logic resolves the

situation (either assert or not assert the flag), the software simulation model cannot reflect

this behavior and mismatch can occur. When using a single clock for RDCLK and WRCLK,

use the FIFO in synchronous mode (EN_SYN = TRUE).

FIFO Applications

A FIFO larger than a single 7 series FPGAs FIFO block can be created by:

• Cascading two or more FIFOs to form a deeper FIFO.

• Building a wider FIFO by connecting two or more FIFOs in parallel.

Cascading FIFOs to Increase Depth

Figure 2-11 shows a way of cascading N FIFO36s to increase depth. The application sets the

first N – 1 FIFOs in FWFT mode and uses external resources to connect them together. The

X-Ref Target - Figure 2-10

Figure 2-10: Resetting All Flags

UG473_c2_10_070110

WRCLK

RST

RDCLK

EMPTY

AEMPTY

FULL

AFULL

RCO_EMPTY

RCO_AEMPTY

RCO_FULL

RCO_AFULL

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