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UG473 (v1.11) November 12, 2014
FIFO Timing Models and Parameters
Clock to Out Delays
T
RCKO_DO
(2)
Clock to data output DO Time after RDCLK that the output data is stable at the
DO outputs of the FIFO. The synchronous FIFO with
DO_REG = 0 is different than in dual-clock mode.
T
RCKO_DO_REG
(2)
Clock to data output DO Time after RDCLK that the output data is stable at the
DO outputs of the FIFO. The synchronous FIFO with
DO_REG = 1 is identical to that in dual-clock mode.
T
RCKO_AEMPTY
(3)
Clock to almost empty
output
AEMPTY Time after RDCLK that the Almost Empty signal is
stable at the ALMOSTEMPTY outputs of the FIFO.
T
RCKO_AFULL
(3)
Clock to almost full
output
AFULL Time after WRCLK that the Almost Full signal is
stable at the ALMOSTFULL outputs of the FIFO.
T
RCKO_EMPTY
(3)
Clock to empty output EMPTY Time after RDCLK that the Empty signal is stable at
the EMPTY outputs of the FIFO.
T
RCKO_FULL
(3)
Clock to full output FULL Time after WRCLK that the Full signal is stable at the
FULL outputs of the FIFO.
T
RCKO_RDERR
(3)
Clock to read error
output
RDERR Time after RDCLK that the Read Error signal is stable
at the RDERR outputs of the FIFO.
T
RCKO_WRERR
(3)
Clock to write error
output
WRERR Time after WRCLK that the Write Error signal is stable
at the WRERR outputs of the FIFO.
T
RCKO_RDCOUNT
(4)
Clock to read pointer
output
RDCOUNT Time after RDCLK that the Read pointer signal is
stable at the RDCOUNT outputs of the FIFO.
T
RCKO_WRCOUNT
(4)
Clock to write pointer
output
WRCOUNT Time after WRCLK that the Write pointer signal is
stable at the WRCOUNT outputs of the FIFO.
Reset to Out
T
RCO_AEMPTY
Reset to almost empty
output
AEMPTY Time after reset that the Almost Empty signal is stable
at the ALMOSTEMPTY outputs of the FIFO.
T
RCO_AFULL
Reset to almost full
output
AFULL Time after reset that the Almost Full signal is stable at
the ALMOSTFULL outputs of the FIFO.
T
RCO_EMPTY
Reset to empty output EMPTY Time after reset that the Empty signal is stable at the
EMPTY outputs of the FIFO.
T
RCO_FULL
Reset to full output FULL Time after reset that the Full signal is stable at the
FULL outputs of the FIFO.
T
RCO_RDERR
Reset to read error
output
RDERR Time after reset that the Read error signal is stable at
the RDERR outputs of the FIFO.
T
RCO_WRERR
Reset to write error
output
WRERR Time after reset that the Write error signal is stable at
the WRERR outputs of the FIFO.
T
RCO_RDCOUNT
Reset to read pointer
output
RDCOUNT Time after reset that the Read pointer signal is stable
at the RDCOUNT outputs of the FIFO.
Table 2-9: FIFO Timing Parameters (Cont’d)
Parameter Function
Control
Signal
Description
- 7 Series FPGAs 1
- Memory Resources 1
- Revision History 2
- RCCK_RST 3
- RCKC_RST 3
- RREC_RST 3
- RREM_RST 3
- Table of Contents 5
- About This Guide 9
- Additional Support Resources 10
- Block RAM Resources 11
- Block RAM Introduction 13
- UG473_c1_01_052610 15
- Read Operation 16
- Write Operation 16
- Write Modes 16
- NO_CHANGE Mode 17
- Conflict Avoidance 18
- Optional Output Registers 19
- Simple Dual-Port Block RAM 20
- Cascadable Block RAM 21
- Byte-Wide Write Enable 21
- RAMB36E1 TDP mode 36 4 22
- RAMB36E1 SDP mode 72 8 22
- RAMB18E1 TDP mode 18 2 22
- RAMB18E1 SDP mode 36 4 22
- Block RAM Library Primitives 23
- Block RAM Port Signals 26
- Set/Reset 27
- Cascade In 29
- Block RAM Address Mapping 30
- Block RAM Attributes 31
- Read Width - READ_WIDTH_[A 33
- Avoidance, page 18 34
- Considerations 35
- Block RAM Applications 37
- Block RAM 38
- Register 38
- Block RAM Timing Model 39
- RCCK_REGCE 40
- RCKC_REGCE 40
- RCKO_DO_REG 40
- Clock Event 1 41
- Clock Event 2 41
- Clock Event 4 41
- Stacked Silicon Interconnect 43
- Built-in FIFO Support 45
- Synchronous FIFO 46
- FIFO Primitives 48
- UG473_c2_04_052610 49
- Standard Mode 51
- UG473_c2_05_052610 51
- Empty Flag 52
- Almost Empty Flag 52
- Read Error Flag 52
- Full Flag 53
- Write Error Flag 53
- Almost Full Flag 53
- FIFO Timing Characteristics 58
- EMPTY Signal 59
- RCCK_WREN 60
- RCKO_AFULL 60
- RCKO_FULL 60
- RCKO_WRERR 61
- RCCK_RDEN 61
- FIFO Applications 64
- UG473_c2_11_052610 65
- 512 x 144 FIFO 66
- UG473_c2_12_052610 66
- UG473_c2_13_052610 67
- Built-in Error Correction 69
- ECC Modes 70
- UG473_c3_01_052610 71
- RAMB36E1 72
- UG473_c3_03_052610 73
- FIFO36E1 73
- ECC Modes of Operation 76
- UG473_c3_06_100610 78
- UG473_c3_07_070110 78
- Standard ECC 79
- Standard ECC Write 80
- Standard ECC Read 80
- Set by Attributes 80
- ECC Encode-Only Write 80
- ECC Encode-Only Read 81
- DO_REG = 0 82
- DO_REG = 1 82
- Encode-Only ECC Write Timing 83
- Encode-Only ECC Read Timing 83
- Decode-Only ECC Write Timing 83
- Decode-Only ECC Read Timing 83
- RCKO_PARITY_ECC 85
- RCKO_SBIT_ECC 85
- RCKO_SBIT_ECC_REG 85
- RCKO_DBIT_ECC 85
- RCKO_DBIT_ECC_REG 85
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