RAM 8.0 BUX II Series Betriebsanweisung PDF herunterladen (Seite 45)

7 Series FPGAs Memory Resources www.xilinx.com 45

UG473 (v1.11) November 12, 2014

Chapter 2

Built-in FIFO Support

Overview

Many FPGA designs use block RAMs to implement FIFOs. In the Xilinx® 7 series

architecture, dedicated logic in the block RAM enables you to implement synchronous or

dual-clock (asynchronous) FIFOs. This eliminates the need for additional CLB logic for

counter, comparator, or status flag generation, and uses just one block RAM resource per

FIFO. Both standard and first-word fall-through (FWFT) modes are supported.

In the 7 series architecture, the FIFO can be configured as a 18 Kb or 36 Kb memory. For the

18 Kb mode, the supported configurations are 4K x 4, 2K x 9, 1K x 18, and 512 x 36. The

supported configurations for the 36 Kb FIFO are 8K x 4, 4K x 9, 2K x 18, 1K x 36, and

512 x 72.

The block RAM can be configured as first-in/first-out (FIFO) memory with common or

independent read and write clocks. Port A of the block RAM is used as a FIFO read port,

and Port B is a FIFO write port. Data is read from the FIFO on the rising edge of read clock

and written to the FIFO on the rising edge of write clock. Independent read and write port

width selection is not supported in FIFO mode without the aid of external CLB logic.

Dual-Clock FIFO

The dual-clock FIFO offers a very simple user interface. The design relies on free-running

write and read clocks, of identical or different frequencies up to the specified maximum

frequency limit. The design avoids any ambiguity, glitch, or metastable problems, even

when the two frequencies are completely unrelated.

The write operation is synchronous, writing the data word available at DI into the FIFO

whenever WREN is active one setup time before the rising WRCLK edge.

The read operation is also synchronous, presenting the next data word at DO whenever the

RDEN is active one setup time before the rising RDCLK edge.

Data flow control is automatic; you need not be concerned about the block RAM

addressing sequence, although WRCOUNT and RDCOUNT are also brought out, if

needed for special applications.

You must, however, observe the FULL and EMPTY flags, and stop writing when FULL is

High, and stop reading when EMPTY is High. If these rules are violated, an active WREN

while FULL is High activates the WRERR flag, and an active RDEN while EMPTY is High

activates the RDERR flag. In either violation, the FIFO content, however, is preserved, and

the address counters stay valid.

Programmable Almost Full and Almost Empty flags are brought out to give you an early

warning when the FIFO is approaching its limits. Both these flag values can be set by

configuration to (almost) anywhere in the FIFO address range.

1 2 ... 40 41 42 43 44 45 46 47 48 49 50 ... 85 86

Keine Kommentare

RAM 8.0 BUX II Series Betriebsanweisung Seite 45