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UG473 (v1.11) November 12, 2014
Block RAM Attributes
Block RAM Attributes
All attribute code examples are discussed in the Block RAM Initialization in VHDL or
Ver i log C ode section. Further information on using these attributes is available in the
Additional RAMB18E1 and RAMB36E1 Primitive Design Considerations section.
Content Initialization - INIT_xx
The memory content can be initialized or cleared in the configuration bitstream. In
previous generation Virtex devices, it was possible to initialize or read back the memory
contents via a blank bitstream. In the 7 series devices, a standard, valid bitstream is
required for block RAM initialization or readback due to the power gating feature. For
more details on initialization and readback of uninstantiated (power gated) block RAM,
see Power Gating of Unused Block RAMs, page 22.
INIT_xx attributes define the initial memory contents. By default, block RAM is initialized
with all zeros during the device configuration sequence. The 64 initialization attributes
from INIT_00 through INIT_3F for the RAMB18E1, and the 128 initialization attributes
from INIT_00 through INIT_7F for the RAMB36E1 represent the regular memory contents.
Each INIT_xx is a 64-digit hex-encoded bit vector. The memory contents can be partially
initialized and are automatically completed with zeros.
The following formula is used to determine the bit positions for each INIT_xx attribute.
Given yy = conversion hex-encoded to decimal (xx), INIT_xx corresponds to the memory
cells as follows:
•from [(yy + 1)× 256] – 1
•to (yy)× 256
For example, for the attribute INIT_1F, the conversion is as follows:
• yy = conversion hex-encoded to decimal (xx) “1F” = 31
• from [(31+1) × 256] – 1 = 8191
•to 31× 256 = 7936
More examples are given in Table 1-15.
Table 1-15: Block RAM Initialization Attributes
Attribute
Memory Location
From To
INIT_00 255 0
INIT_01 511 256
INIT_02 767 512
…… …
INIT_0E 3839 3584
INIT_0F 4095 3840
INIT_10 4351 4096
…… …
INIT_1F 8191 7936
INIT_20 8447 8192
- 7 Series FPGAs 1
- Memory Resources 1
- Revision History 2
- RCCK_RST 3
- RCKC_RST 3
- RREC_RST 3
- RREM_RST 3
- Table of Contents 5
- About This Guide 9
- Additional Support Resources 10
- Block RAM Resources 11
- Block RAM Introduction 13
- UG473_c1_01_052610 15
- Read Operation 16
- Write Operation 16
- Write Modes 16
- NO_CHANGE Mode 17
- Conflict Avoidance 18
- Optional Output Registers 19
- Simple Dual-Port Block RAM 20
- Cascadable Block RAM 21
- Byte-Wide Write Enable 21
- RAMB36E1 TDP mode 36 4 22
- RAMB36E1 SDP mode 72 8 22
- RAMB18E1 TDP mode 18 2 22
- RAMB18E1 SDP mode 36 4 22
- Block RAM Library Primitives 23
- Block RAM Port Signals 26
- Set/Reset 27
- Cascade In 29
- Block RAM Address Mapping 30
- Block RAM Attributes 31
- Read Width - READ_WIDTH_[A 33
- Avoidance, page 18 34
- Considerations 35
- Block RAM Applications 37
- Block RAM 38
- Register 38
- Block RAM Timing Model 39
- RCCK_REGCE 40
- RCKC_REGCE 40
- RCKO_DO_REG 40
- Clock Event 1 41
- Clock Event 2 41
- Clock Event 4 41
- Stacked Silicon Interconnect 43
- Built-in FIFO Support 45
- Synchronous FIFO 46
- FIFO Primitives 48
- UG473_c2_04_052610 49
- Standard Mode 51
- UG473_c2_05_052610 51
- Empty Flag 52
- Almost Empty Flag 52
- Read Error Flag 52
- Full Flag 53
- Write Error Flag 53
- Almost Full Flag 53
- FIFO Timing Characteristics 58
- EMPTY Signal 59
- RCCK_WREN 60
- RCKO_AFULL 60
- RCKO_FULL 60
- RCKO_WRERR 61
- RCCK_RDEN 61
- FIFO Applications 64
- UG473_c2_11_052610 65
- 512 x 144 FIFO 66
- UG473_c2_12_052610 66
- UG473_c2_13_052610 67
- Built-in Error Correction 69
- ECC Modes 70
- UG473_c3_01_052610 71
- RAMB36E1 72
- UG473_c3_03_052610 73
- FIFO36E1 73
- ECC Modes of Operation 76
- UG473_c3_06_100610 78
- UG473_c3_07_070110 78
- Standard ECC 79
- Standard ECC Write 80
- Standard ECC Read 80
- Set by Attributes 80
- ECC Encode-Only Write 80
- ECC Encode-Only Read 81
- DO_REG = 0 82
- DO_REG = 1 82
- Encode-Only ECC Write Timing 83
- Encode-Only ECC Read Timing 83
- Decode-Only ECC Write Timing 83
- Decode-Only ECC Read Timing 83
- RCKO_PARITY_ECC 85
- RCKO_SBIT_ECC 85
- RCKO_SBIT_ECC_REG 85
- RCKO_DBIT_ECC 85
- RCKO_DBIT_ECC_REG 85
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