RAM 8.0 BUX II Series Betriebsanweisung PDF herunterladen (Seite 60)

60 www.xilinx.com 7 Series FPGAs Memory Resources

UG473 (v1.11) November 12, 2014

Chapter 2: Built-in FIFO Support

Case 2: Writing to a Full or Almost Full FIFO

Prior to the operations performed in Figure 2-7, the FIFO is almost completely full. In this

example, the timing diagram reflects of both standard and FWFT modes.

Clock Event 1: Write Operation and Assertion of Almost Full Signal

During a write operation to an almost full FIFO, the Almost Full signal is asserted.

• At time T

RDCK_DI

, before clock event 1 (WRCLK), data 00 becomes valid at the DI

inputs of the FIFO.

• At time T

RCCK_WREN

, before clock event 1 (WRCLK), write enable becomes valid at

the WREN input of the FIFO.

• At time T

RCKO_AFULL

, one clock cycle after clock event 1 (WRCLK), Almost Full is

asserted at the AFULL output pin of the FIFO.

Clock Event 2: Write Operation and Assertion of Full Signal

The FULL signal pin is asserted when the FIFO is full.

• At time T

RDCK_DI

, before clock event 2 (WRCLK), data 04 becomes valid at the DI

inputs of the FIFO.

• Write enable remains asserted at the WREN input of the FIFO.

• At time T

RCKO_FULL

, after clock event 2 (WRCLK), Full is asserted at the FULL output

pin of the FIFO.

If the FIFO is full, and a read followed by a write is performed, the write might not be

successful, depending on the timing between read and write. Consult the simulation

model for the exact behavior.

X-Ref Target - Figure 2-7

Figure 2-7: Writing to a Full / Almost Full FIFO

UG473_c2_07_070110

00 01 02 03 04 05 06

WRCLK

WREN

RDCLK

RDEN

FULL

AFULL

WRERR

1 42

RDCK_DI

RCKO_AFULL

RCKO_WERR

RCKO_FULL

RCCK_WREN

RCKO_WERR

RCCK_WREN

1 2 ... 55 56 57 58 59 60 61 62 63 64 65 ... 85 86

Kommentare zu diesen Handbüchern

Keine Kommentare

RAM 8.0 BUX II Series Betriebsanweisung Seite 60

Kommentare zu diesen Handbüchern

Verwandte Produkte und Handbücher für Audioverstärker RAM 8.0 BUX II Series