RAM 4.5 BUX II Series Bedienungsanleitung PDF herunterladen (Seite 41)

DE1 User Manual

Signal Name FPGA Pin No. Description

AUD_ADCLRCK PIN_A6 Audio CODEC ADC LR Clock

AUD_ADCDAT PIN_B6 Audio CODEC ADC Data

AUD_DACLRCK PIN_A5 Audio CODEC DAC LR Clock

AUD_DACDAT PIN_B5 Audio CODEC DAC Data

AUD_XCK PIN_B4 Audio CODEC Chip Clock

AUD_BCLK PIN_A4 Audio CODEC Bit-Stream Clock

I2C_SCLK PIN_A3 I2C Data

I2C_SDAT PIN_B3 I2C Clock

Table 4.9. Audio CODEC pin assignments.

4.8 RS-232 Serial Port

The DE1 board uses the MAX232 transceiver chip and a 9-pin D-SUB connector for RS-232

communications. For detailed information on how to use the transceiver refer to the datasheet,

which is available on the manufacturer’s web site, and from the Datasheet folder on the DE1

System CD-ROM. Figure 4.16 shows the related schematics, and Table 4.10 lists the Cyclone II

FPGA pin assignments.

Figure 4.16. MAX232 (RS-232) chip schematic.

Signal Name FPGA Pin No. Description

UART_RXD PIN_F14 UART Receiver

UART_TXD PIN_G12 UART Transmitter

Table 4.10. RS-232 pin assignments.

1 2 ... 36 37 38 39 40 41 42 43 44 45 46 ... 55 56

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RAM 4.5 BUX II Series Bedienungsanleitung Seite 41