RAM 4.5 BUX II Series Bedienungsanleitung PDF herunterladen (Seite 27)

DE1 User Manual

Figure 4.1 illustrates the JTAG configuration setup. To download a configuration bit stream into the

Cyclone II FPGA, perform the following steps:

• Ensure that power is applied to the DE1 board

• Connect the supplied USB cable to the USB Blaster port on the DE1 board (see Figure 2.1)

• Configure the JTAG programming circuit by setting the RUN/PROG switch (on the left side

of the board) to the RUN position.

• The FPGA can now be programmed by using the Quartus II Programmer module to select a

configuration bit stream file with the .sof filename extension

FPGA

USB Blaster Circuit

EPCS4

Serial

Configuration

Device

JTAG Config Port

USB

JTAG Config Signals

Auto

Power-on Config

MAX

3128

Quartus II

Programmer JTAG UART

PROG/RUN

"RUN"

Figure 4.1. The JTAG configuration scheme.

Configuring the EPCS4 in AS Mode

Figure 4.2 illustrates the AS configuration set up. To download a configuration bit stream into the

EPCS4 serial EEPROM device, perform the following steps:

• Ensure that power is applied to the DE1 board

• Connect the supplied USB cable to the USB Blaster port on the DE1 board (see Figure 2.1)

• Configure the JTAG programming circuit by setting the RUN/PROG switch (on the left side

of the board) to the PROG position.

• The EPCS4 chip can now be programmed by using the Quartus II Programmer module to

select a configuration bit stream file with the .pof filename extension

• Once the programming operation is finished, set the RUN/PROG switch back to the RUN

position and then reset the board by turning the power switch off and back on; this action

causes the new configuration data in the EPCS4 device to be loaded into the FPGA chip.

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RAM 4.5 BUX II Series Bedienungsanleitung Seite 27