RAM 4.5 BUX II Series Bedienungsanleitung Seite 1

Altera DE1 Board DE1 Development and Education Board User Manual Version 1.1 Copyright © 2006 Altera Corporation

DE1 User Manual 8 • Applications for MP3 players and recorders, PDAs, smart phones, voice recorders, etc. VGA output • Uses a 4-bit resistor-net

DE1 User Manual 9 • All user LEDs are flashing • All 7-segment displays are cycling through the numbers 0 to F • The VGA monitor displays the

DE1 User Manual 10 Chapter 3 DE1 Control Panel The DE1 board comes with a Control Panel facility that allows a user to access various components

DE1 User Manual 11 7. The Control Panel is now ready for use; experiment by setting the value of some 7-segment display and observing the result

DE1 User Manual 12 issue commands to the control circuitry. The provided IP handles all requests and performs data transfers between the computer

DE1 User Manual 13 Figure 3.4. Controlling LEDs and the LCD display. 3.3 SDRAM/SRAM Controller and Programmer The Control Panel can be used

DE1 User Manual 14 A 16-bit word can be written into the SDRAM by entering the address of the desired location, specifying the data to be written,

DE1 User Manual 15 • Read one byte from the memory • Write a binary file to the memory • Load the contents of the Flash memory into a file

DE1 User Manual 16 To read a byte of data from a random location, enter the address of the location and click on the Read button. The rDATA box wi

DE1 User Manual 17 To let users implement and test their IP cores (written in Verilog) without requiring them to implement complex API/Host contro

Altera DE1 Board ii CONTENTS Chapter 1 DE1 Package...

DE1 User Manual 18 3.6 TOOLS – Multi-Port SRAM/SDRAM/Flash Controller The TOOLS page of the Control Panel GUI allows selection of the User Ports.

DE1 User Manual 19 played from the Audio DAC circuit. 6. Note that the Asynchronous Port 1 is connected to the Audio DAC part, as shown in Figure

DE1 User Manual 20 The image in Figure 3.9 is stored in an M4K memory block in the Cyclone II FPGA. It is loaded into the M4K block in the MIF/Hex

DE1 User Manual 21 Figure 3.11. Multi-Port Controller configured to display an image from the SRAM. Figure 3.12. A displayed image.

DE1 User Manual 22 You can display any image file by loading it into the SRAM chip or into an M4K memory block in the Cyclone II chip. This requir

DE1 User Manual 23 Image Source R/G/B Band Filter B&W Threshold Filter Output Result (640x480) Color Picture R/G/B N/A Raw_Data_Gray Color

DE1 User Manual 24 Chapter 4 Using the DE1 Board This chapter gives instructions for using the DE1 board and describes each of its I/O devices.

DE1 User Manual 25 Figure 4.1 illustrates the JTAG configuration setup. To download a configuration bit stream into the Cyclone II FPGA, perform t

DE1 User Manual 26 FPGAUSB Blaster CircuitEPCS4SerialConfigurationDeviceJTAG Config Port USBAutoPower-on Config MAX3128Quartus IIProgrammerAS Mod

DE1 User Manual 27 There are 27 user-controllable LEDs on the DE1 board. Eighteen red LEDs are situated above the 18 toggle switches, and eight gr

DE1 User Manual 1 Chapter 1 DE1 Package The DE1 package contains all components needed to use the DE1 board in conjunction with a computer that r

DE1 User Manual 28 Figure 4.5. Schematic diagram of the LEDs. Signal Name FPGA Pin No. Description SW[0] PIN_L22 Toggle Switch[0] SW[1] PIN_

DE1 User Manual 29 SW[8] PIN_M1 Toggle Switch[8] SW[9] PIN_L2 Toggle Switch[9] Table 4.1. Pin assignments for the toggle switches. Signal N

DE1 User Manual 30 4.3 Using the 7-segment Displays The DE1 Board has four 7-segment displays. These displays are arranged into a group of four,

DE1 User Manual 31 Signal Name FPGA Pin No. Description HEX0[0] PIN_J2 Seven Segment Digit 0[0] HEX0[1] PIN_J1 Seven Segment Digit 0[1] HEX0[

DE1 User Manual 32 Figure 4.8. Schematic diagram of the clock circuit. Signal Name FPGA Pin No. Description CLOCK_27 PIN_D12, PIN_E12 27 M

DE1 User Manual 33 Figure 4.10. Schematic diagram of the expansion headers. Signal Name FPGA Pin No. Description GPIO_0[0] PIN_A13 GPIO Co

DE1 User Manual 34 GPIO_0[1] PIN_B13 GPIO Connection 0[1] GPIO_0[2] PIN_A14 GPIO Connection 0[2] GPIO_0[3] PIN_B14 GPIO Connection 0[3] GPIO_0[

DE1 User Manual 35 GPIO_1[2] PIN_H14 GPIO Connection 1[2] GPIO_1[3] PIN_G15 GPIO Connection 1[3] GPIO_1[4] PIN_E14 GPIO Connection 1[4] GPIO

DE1 User Manual 36 4.6 Using VGA The DE1 board includes a 16-pin D-SUB connector for VGA output. The VGA synchronization signals are provided dir

DE1 User Manual 37 During the data display interval the RGB data drives each pixel in turn across the row being displayed. Finally, there is a tim

DE1 User Manual 2 • CD-ROMs containing Altera’s Quartus® II 6.0 Web Edition software and the Nios® II 5.0 embedded processor • Bag of six rubber

DE1 User Manual 38 VGA_B[0] PIN_A9 VGA Blue[0] VGA_B[1] PIN_D11 VGA Blue[1] VGA_B[2] PIN_A10 VGA Blue[2] VGA_B[3] PIN_B10 VGA Blue[3] VGA_HS P

DE1 User Manual 39 Signal Name FPGA Pin No. Description AUD_ADCLRCK PIN_A6 Audio CODEC ADC LR Clock AUD_ADCDAT PIN_B6 Audio CODEC ADC Data AU

DE1 User Manual 40 4.9 PS/2 Serial Port The DE1 board includes a standard PS/2 interface and a connector for a PS/2 keyboard or mouse. Figure 4.1

DE1 User Manual 41 Figure 4.23. SDRAM schematic. Figure 4.24. SRAM schematic.

DE1 User Manual 42 Figure 4.25. Flash schematic. Signal Name FPGA Pin No. Description DRAM_ADDR[0] PIN_W4 SDRAM Address[0] DRAM_ADDR[1] PIN_W

DE1 User Manual 43 DRAM_DQ[7] PIN_Y2 SDRAM Data[7] DRAM_DQ[8] PIN_N1 SDRAM Data[8] DRAM_DQ[9] PIN_N2 SDRAM Data[9] DRAM_DQ[10] PIN_P1 SDRAM Da

DE1 User Manual 44 SRAM_ADDR[14] PIN_R10 SRAM Address[14] SRAM_ADDR[15] PIN_T7 SRAM Address[15] SRAM_ADDR[16] PIN_Y6 SRAM Address[16] SRAM_ADDR

DE1 User Manual 45 FL_ADDR[8] PIN_R14 FLASH Address[8] FL_ADDR[9] PIN_Y13 FLASH Address[9] FL_ADDR[10] PIN_R12 FLASH Address[10] FL_ADDR[11] PI

DE1 User Manual 46 Chapter 5 Examples of Advanced Demonstrations This chapter provides a number of examples of advanced circuits implemented on t

DE1 User Manual 47 • Power on the DE1 board, with the USB cable connected to the USB Blaster port. If necessary (that is, if the default factory

DE1 User Manual 3 1.3 Getting Help Here are the addresses where you can get help if you encounter problems: • Altera Corporation 101 Innovation

DE1 User Manual 48 The audio codec used on the DE1 board has two channels, which can be turned ON/OFF using SW1 and SW2. Figure 5.1. The Setup

DE1 User Manual 49 Demonstration Setup, File Locations, and Instructions • Project directory: DE1_Synthesizer • Bit stream used: DE1_Synthesizer

DE1 User Manual 50 I #4 K 5 O #5 L 6 P #6 : 7 “ +1 Figure 5.3. Usage of the Key 5.3 A Karaoke Machine This demonstration uses the microphone-

DE1 User Manual 51 Demonstration Setup, File Locations, and Instructions • Project directory: DE1_i2sound • Bit stream used: DE1_i2sound.sof or

DE1 User Manual 52 5.4 SD Card Music Player Many commercial media/audio players use a large external storage device, such as an SD card or CF car

DE1 User Manual 53 Demonstration Setup, File Locations, and Instructions • Project directory: DE1_SD_Card_Audio • Bit stream used: DE1_SD_Card_A

DE1 User Manual 54 Copyright © 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo

DE1 User Manual 4 Chapter 2 Altera DE1 Board This chapter presents the features and design characteristics of the DE1 board. 2.1 Layout and Com

DE1 User Manual 5 The following hardware is provided on the DE1 board: • Altera Cyclone® II 2C20 FPGA device • Altera Serial Configuration dev

DE1 User Manual 6 2.2 Block Diagram of the DE1 Board Figure 2.2 gives the block diagram of the DE1 board. To provide maximum flexibility for the

DE1 User Manual 7 • 512-Kbyte Static RAM memory chip • Organized as 256K x 16 bits • Accessible as memory for the Nios II processor and by the