RAM 6.0 BUX II Series Betriebsanweisung PDF herunterladen (Seite 9)

4. Architecture Considerations

take tens of uninterruptable microseconds. The operating system and application

also contribute to interrupt latency by inhibiting the processor’s ability to receive

interrupts. While each VxWorks architecture port has optimized these interrupt

locks to an absolute minimum, be aware that some variation in performance exists

when comparing one architecture to another.

Non-maskable interrupts should not be used. On some architectures, they may be

usable, provided that they do not call any VxWorks kernel routines as part of the

service routine. However, on other architectures, they cannot be used for anything

other than system reboot.

Cache Issues

Many architectures have instruction and data caching to increase processor

performance and reduce CPU bus activity. The most difficult aspect of memory

caching is that the technology has often addressed the cache coherency problem

inadequately.

The cache coherency problem refers to cached information that is redundant with

the information in memory. If another bus master or DMA device updates

memory, the cached data no longer reflects the actual value in memory. Without

sufficient hardware support, solving the coherency problem is left to the software.

Unfortunately, cache management varies greatly from architecture to architecture.

In some cases, the architecture provides cache management instructions; in others,

cache management is bundled together with functions for managing virtual

memory.

VxWorks provides a cache library interface that is unified across disparate CPU

architectures. This permits highly portable, high-performance device drivers to be

implemented with VxWorks. For more information, see the reference entry for

cacheLib.

When considering hardware snooping, only full cache snooping is of benefit. Some

processors implement partial snooping, but partial snooping does not meet

common memory coherency requirements. Only when the snoop hardware makes

the memory fully coherent is it useful for VxWorks.

The combination of copyback cache without snooping is particularly dangerous,

although the risk is reduced if all user buffers are positioned so that they do not

share cache lines with any other buffer.

The user can protect the rear end of any buffer by increasing the size of the memory

request by one cache line. This guarantees that no other buffer shares a cache line

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RAM 6.0 BUX II Series Betriebsanweisung Seite 9