RAM 6.0 BUX II Series Betriebsanweisung PDF herunterladen (Seite 16)

VxWorks

Hardware Considerations Guide, 6.0

most applications, this is not a problem. However, for applications with extremely

low latency requirements, this can be ameliorated somewhat by locating device

buffers in VME memory.

Read-Modify-Write (RMW)

Read-modify-write (RMW) must be provided in an indivisible manner.

The board must adhere to the RMW mechanism defined in the VME specification;

namely, a master must keep the address strobe low between the read and the write

portions of the cycle. A correctly functioning dual-ported slave board keeps the

RMW indivisible across both ports by detecting an address strobe that remains

low.

Unfortunately, keeping the address strobe low is only viable if you are reading and

writing the same single address. A more complicated indivisible instruction, such

as CAS, that involves multiple addresses cannot use this, and thus has no correct

mechanism for dual-ported memory. Because VxWorks uses only TAS, this is not

an issue. Some vendors have added a LOCK pin to the P2 bus for this reason.

However, the pin is not part of the standard and is therefore insufficient support

for this mechanism. For most boards, this is not an issue.

Caching and/or snooping can be an issue for VME RMW cycles. The shared

memory master board must not introduce any cache coherency problems. It must

be non-cached, or protected by full snooping capabilities, in order to handle proper

VME slave accesses.

For some PowerPC implementations, it has been necessary to use bus arbitration

as a global semaphore for VME RMW operations. When a board cannot generate,

nor respond, to RMW cycles, using the bus as a global semaphore works. Any

board that cannot use RMW, arbitrates for and holds the VME bus while a read and

write cycle is completed. In addition, the bus master board, where the shared

objects are stored, must implement the same bus lockup protection, even if the

master board can do RMW cycles correctly. This scheme is implemented in the BSP

sysBusTas( ) and sysBusTasClear( ) functions.

Arbitration

The board should default to bus request level 3 and provide a jumper mechanism

if alternative arbitration levels are supported.

It is often convenient to be able to select the manner of bus-release that can be RWD

(release when done), ROR (release on request), or RAT (release after timeout).

1 2 ... 11 12 13 14 15 16 17 18 19 20 21 ... 35 36

Keine Kommentare

RAM 6.0 BUX II Series Betriebsanweisung Seite 16