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PPP and ATM Termination Type C RAM Package Release 1.4.1

Freescale Semiconductor 7

Table 11. Revision History—Revision 0.0.3

Release 0.0.3

New Features

none

Bug Fixes

When the Ethernet receive is highly loaded with in coming frames it might stop functioning at all.

This bug is valid only if the next two conditions take place:

1. More than one threads are enabled.

2. The maximum length of the incoming frames is longer than 4*(VFIFO block size). (VFIFO block size =

128 up to 248).

When using Init_MUX/Init_DeMUX host command it might corrupt the page of anther thread.

Table 12. Revision History—Revision 0.0.2

Release 0.0.2

New Features

Ethernet Hierarchical schedule (HES) work conserving mode. Programing model would be released in the

next specification document

New bit was added in LMR register called RxMLDis which is located at position 4. If set, all frames which

contain MLMC PPP PID will be dropped and ILLEGAL FRAME counter under this link will be incremented.

Bug Fixes

MLMC frame received with length =< 8 Bytes with ACC Error, may result in illegal DMA (Buss Error).

MLMC frame received with length=< (expected header size + FCS) results in illegal DMA (Buss Error).

MLMC frame with header = 9Bytes will result in an unexpected behavior.

MLMC frame received with length =< 8 Bytes after long frame may result in losing the long frame.

When FBPBusy, PRTBusy, Fragment loss conditions occurs, the rest of the MLMC frames arrive for that

class will never be enqueued to the PRT.

Copy2CPU option is not allowed. It might cause a halt of the system.

In interworking the IW Error Interrupt in register IWEMODER has to be masked. {IWEMODER[26]==0}.

In interworking, when an Ethernet frame is directed only to a termination queue {Only to CPU} HM is not

supported.

Table 13. Revision History—Revision 0.0.1

Release 0.0.1

New Features

A mechanism was added in PPP MUX programming model that allows performing a graceful stop of the

MUX operation

The maximum number of MUX Tx queues in ML PPP was increased to 32. In addition, a multi-threading

mechanism was introduced for PPP MUX operation

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