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10 TMS320C6457 Fixed-Point Digital Signal Processor Silicon Errata SPRZ293A—November 2009

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Advisory 2 EDMA3CC COMPACTV Issue

Revision(s) Affected: 1.1, 1.0.

Details: A bug has been found inside the EDMA3 channel controller (EDMA3CC). The logic

for decrementing the completion request active (COMPACTV) counter is incorrect for

devices having six or more EDMA3 transfer controllers (EDMA3TCs). Therefore, the

C6457 device is affected by this bug.

The COMPACTV field inside the channel controller status register (CCSTAT)

indicates the count for the number of outstanding transfer requests requiring

completion status that have been submitted to the transfer controllers. The channel

controller increments this count every time a transfer request (TR) is submitted and is

programmed to report completion (the TCINTEN or TCCHEN, or the ITCINTEN or

ITCCHEN bits in OPT in the parameter entry associated with the TR are set). The

counter decrements for every valid transfer completion code (TCC) received back from

the transfer controllers. The bug occurs because the channel controller decrements the

counter by an insufficient value when multiple responses are received concurrently

from multiple (two or more) transfer controllers. Thus, the counter may gradually

increase over time until it saturates at 0x3F.

If at any time the count reaches a value of 0x3F, the channel controller does not service

new TRs until the count is less than 0x3F (which will happen when a transfer

completion code is received from a transfer controller for an in-flight request). Once

the state is reached where the counter is close to the saturation value of 0x3F, the

performance of the EDMA decreases dramatically. This decreased performance

happens because the channel controller will artificially limit its number of TRs in flight

to the COMPACTV saturation value thereby preventing full usage of the available TCs.

When the count reaches 0x3F, the TCCERR bit is set in the channel controller error

Workaround: The workaround is achieved by having the DSP directly program one of the transfer

controllers (bypassing the channel controller) with a transfer request that requires

completion. This request avoids the COMPACTV increment (because TC is

programmed directly) and forces a COMPACTV decrement when the TC responds to

the CC with the completion signaling.

A specific transfer controller and a specific TCC value should be dedicated in the

system for this workaround. TC4 or TC5 is suggested because their connectivity is

identical. However, the specific TC should be selected based on the end-system usage.

The DSP should poll the COMPACTV field often enough such that the counter is not

allowed to exceed 0x30. The actual COMPACTV polling interval may need to be set

through experimentation on the specific end system, because the rate of increment of

the counter is system- and load-specific.

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